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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Greentime Hu =E6=96=BC 2021=E5=B9=B44=E6=9C=8819= =E6=97=A5 =E9=80=B1=E4=B8=80 =E4=B8=8A=E5=8D=8810:43=E5=AF=AB=E9=81=93=EF= =BC=9A > > Palmer Dabbelt =E6=96=BC 2021=E5=B9=B43=E6=9C=8831= =E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8A=E5=8D=888:24=E5=AF=AB=E9=81=93=EF=BC= =9A > > > > On Wed, 17 Mar 2021 23:08:13 PDT (-0700), greentime.hu@sifive.com wrote= : > > > Signed-off-by: Greentime Hu > > > --- > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 34 ++++++++++++++++++++= ++ > > > 1 file changed, 34 insertions(+) > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/= boot/dts/sifive/fu740-c000.dtsi > > > index d1bb22b11920..d0839739b425 100644 > > > --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > @@ -158,6 +158,7 @@ prci: clock-controller@10000000 { > > > reg =3D <0x0 0x10000000 0x0 0x1000>; > > > clocks =3D <&hfclk>, <&rtcclk>; > > > #clock-cells =3D <1>; > > > + #reset-cells =3D <1>; > > > }; > > > uart0: serial@10010000 { > > > compatible =3D "sifive,fu740-c000-uart", "sifiv= e,uart0"; > > > @@ -288,5 +289,38 @@ gpio: gpio@10060000 { > > > clocks =3D <&prci PRCI_CLK_PCLK>; > > > status =3D "disabled"; > > > }; > > > + pcie@e00000000 { > > > + #address-cells =3D <3>; > > > + #interrupt-cells =3D <1>; > > > + #num-lanes =3D <8>; > > > + #size-cells =3D <2>; > > > + compatible =3D "sifive,fu740-pcie"; > > > + reg =3D <0xe 0x00000000 0x1 0x0 > > > + 0xd 0xf0000000 0x0 0x10000000 > > > + 0x0 0x100d0000 0x0 0x1000>; > > > + reg-names =3D "dbi", "config", "mgmt"; > > > + device_type =3D "pci"; > > > + dma-coherent; > > > + bus-range =3D <0x0 0xff>; > > > + ranges =3D <0x81000000 0x0 0x60080000 0x0 0x6= 0080000 0x0 0x10000 /* I/O */ > > > + 0x82000000 0x0 0x60090000 0x0 0x600= 90000 0x0 0xff70000 /* mem */ > > > + 0x82000000 0x0 0x70000000 0x0 0x700= 00000 0x0 0x1000000 /* mem */ > > > + 0xc3000000 0x20 0x00000000 0x20 0x000= 00000 0x20 0x00000000>; /* mem prefetchable */ > > > + num-lanes =3D <0x8>; > > > + interrupts =3D <56 57 58 59 60 61 62 63 64>; > > > + interrupt-names =3D "msi", "inta", "intb", "int= c", "intd"; > > > + interrupt-parent =3D <&plic0>; > > > + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; > > > + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic0 57>, > > > + <0x0 0x0 0x0 0x2 &plic0 58>, > > > + <0x0 0x0 0x0 0x3 &plic0 59>, > > > + <0x0 0x0 0x0 0x4 &plic0 60>; > > > + clock-names =3D "pcie_aux"; > > > + clocks =3D <&prci PRCI_CLK_PCIE_AUX>; > > > + pwren-gpios =3D <&gpio 5 0>; > > > + perstn-gpios =3D <&gpio 8 0>; > > > + resets =3D <&prci 4>; > > > + status =3D "okay"; > > > + }; > > > }; > > > }; > > > > Acked-by: Palmer Dabbelt > > > > I'm happy to take these all through the RISC-V tree if that helps, but > > as usual I'd like reviews or acks from the subsystem maintainers. It > > looks like there are some issues so I'm going to drop this from my > > inbox. > > Hi Palmer, > > Since the subsystem maintainer has pick the first 5 patches to his > branch, would you please help to pick the 6th patch of version 6? Sorry there is no version 6, I mean version 5. :p > Thank you. :) > > https://www.spinics.net/lists/linux-clk/msg57213.html > https://patchwork.kernel.org/project/linux-riscv/patch/20210406092634.504= 65-7-greentime.hu@sifive.com/