From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Andy Shevchenko <andy@infradead.org>,
alexander.h.duyck@intel.com,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH 1/3] pci: Add Designated Vendor Specific Capability
Date: Tue, 5 May 2020 11:49:51 +0300 [thread overview]
Message-ID: <CAHp75VcAA3DmjZnnpg=XdiKWtWWZBXeOguqEC7JSNYZmawCYSg@mail.gmail.com> (raw)
In-Reply-To: <20200505013206.11223-2-david.e.box@linux.intel.com>
On Tue, May 5, 2020 at 4:32 AM David E. Box <david.e.box@linux.intel.com> wrote:
>
> Add pcie dvsec extended capability id along with helper macros to
pcie -> PCIe
dvsec -> DVSEC (but here I'm not sure, what's official abbreviation for this?)
> retrieve information from the headers.
> https://members.pcisig.com/wg/PCI-SIG/document/12335
Perhaps
DocLink: ...
(as a tag)
>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> ---
> include/uapi/linux/pci_regs.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index f9701410d3b5..c96f08d1e711 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -720,6 +720,7 @@
> #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
> #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
> #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
> +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Desinated Vendor-Specific */
> #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
> #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
> #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
> @@ -1062,6 +1063,10 @@
> #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */
> #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */
>
> +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */
> +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */
> +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */
> +
> /* Data Link Feature */
> #define PCI_DLF_CAP 0x04 /* Capabilities Register */
> #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */
> --
> 2.20.1
>
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2020-05-05 8:50 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200505013206.11223-1-david.e.box@linux.intel.com>
2020-05-05 1:32 ` [PATCH 1/3] pci: Add Designated Vendor Specific Capability David E. Box
2020-05-05 8:49 ` Andy Shevchenko [this message]
2020-05-05 15:00 ` David E. Box
2020-05-05 16:34 ` Bjorn Helgaas
2020-05-05 2:31 ` [PATCH 2/3] mfd: Intel Platform Monitoring Technology support David E. Box
2020-05-05 2:31 ` [PATCH 3/3] platform/x86: Intel PMT Telemetry capability driver David E. Box
2020-05-05 13:49 ` Andy Shevchenko
2020-05-05 21:09 ` David E. Box
2020-05-08 2:33 ` David E. Box
2020-05-05 2:53 ` [PATCH 2/3] mfd: Intel Platform Monitoring Technology support Randy Dunlap
2020-05-05 14:55 ` David E. Box
2020-05-05 9:02 ` Andy Shevchenko
2020-05-05 15:15 ` David E. Box
2020-05-08 2:18 ` [PATCH v2 0/3] Intel Platform Monitoring Technology David E. Box
2020-05-08 9:59 ` Andy Shevchenko
2020-07-14 6:23 ` [PATCH V3 " David E. Box
2020-07-17 19:06 ` [PATCH V4 " David E. Box
2020-07-27 10:23 ` Andy Shevchenko
2020-07-27 16:29 ` David E. Box
2020-07-29 21:37 ` [PATCH V5 " David E. Box
2020-08-10 14:15 ` David E. Box
2020-08-10 14:42 ` Umesh A
2020-08-11 8:04 ` Lee Jones
2020-08-11 14:50 ` David E. Box
2020-07-29 21:37 ` [PATCH V5 1/3] PCI: Add defines for Designated Vendor-Specific Extended Capability David E. Box
2020-07-29 21:37 ` [PATCH V5 2/3] mfd: Intel Platform Monitoring Technology support David E. Box
2020-07-29 21:37 ` [PATCH V5 3/3] platform/x86: Intel PMT Telemetry capability driver David E. Box
2020-07-17 19:06 ` [PATCH V4 1/3] PCI: Add defines for Designated Vendor-Specific Extended Capability David E. Box
2020-07-17 20:11 ` Andy Shevchenko
2020-07-17 19:06 ` [PATCH V4 2/3] mfd: Intel Platform Monitoring Technology support David E. Box
2020-07-28 7:58 ` Lee Jones
2020-07-28 20:35 ` David E. Box
2020-07-29 22:59 ` Mark D Rustad
2020-07-30 17:53 ` David E. Box
2020-07-31 6:19 ` Lee Jones
2020-07-17 19:06 ` [PATCH V4 3/3] platform/x86: Intel PMT Telemetry capability driver David E. Box
2020-07-14 6:23 ` [PATCH V3 1/3] PCI: Add defines for Designated Vendor-Specific Capability David E. Box
2020-07-14 8:40 ` Andy Shevchenko
2020-07-16 2:55 ` Randy Dunlap
2020-07-16 15:07 ` Bjorn Helgaas
2020-07-16 15:07 ` Randy Dunlap
2020-07-16 17:18 ` Alexander Duyck
2020-07-16 18:31 ` David E. Box
2020-07-14 6:23 ` [PATCH V3 2/3] mfd: Intel Platform Monitoring Technology support David E. Box
2020-07-14 6:23 ` [PATCH V3 3/3] platform/x86: Intel PMT Telemetry capability driver David E. Box
2020-07-14 8:51 ` Andy Shevchenko
2020-07-15 7:39 ` Alexey Budankov
2020-07-15 23:59 ` David E. Box
2020-07-16 5:57 ` Alexey Budankov
2020-07-16 2:57 ` Randy Dunlap
2020-05-08 2:18 ` [PATCH v2 1/3] PCI: Add defines for Designated Vendor-Specific Capability David E. Box
2020-05-08 2:18 ` [PATCH v2 2/3] mfd: Intel Platform Monitoring Technology support David E. Box
2020-05-08 9:15 ` Andy Shevchenko
2020-05-08 2:18 ` [PATCH v2 3/3] platform/x86: Intel PMT Telemetry capability driver David E. Box
2020-05-08 9:57 ` Andy Shevchenko
2020-05-09 16:27 ` David E. Box
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