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From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Srinath Mannam <srinath.mannam@broadcom.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Ray Jui <rjui@broadcom.com>, Rob Herring <robh+dt@kernel.org>,
	Andrew Murray <andrew.murray@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	bcm-kernel-feedback-list <bcm-kernel-feedback-list@broadcom.com>,
	linux-pci@vger.kernel.org,
	devicetree <devicetree@vger.kernel.org>,
	linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Ray Jui <ray.jui@broadcom.com>
Subject: Re: [PATCH v5 2/6] PCI: iproc: Add INTx support with better modeling
Date: Thu, 26 Mar 2020 16:37:15 +0200	[thread overview]
Message-ID: <CAHp75VfUCwcXN_OF-tq1wuiCFdicMMEpJpWNccQT=6cv0DNnWQ@mail.gmail.com> (raw)
In-Reply-To: <1585205326-25326-3-git-send-email-srinath.mannam@broadcom.com>

On Thu, Mar 26, 2020 at 8:49 AM Srinath Mannam
<srinath.mannam@broadcom.com> wrote:
>
> From: Ray Jui <ray.jui@broadcom.com>
>
> Add PCIe legacy interrupt INTx support to the iProc PCIe driver by
> modeling it with its own IRQ domain. All 4 interrupts INTA, INTB, INTC,
> INTD share the same interrupt line connected to the GIC in the system,
> while the status of each INTx can be obtained through the INTX CSR
> register.

...
> +       val &= ~(BIT(irqd_to_hwirq(d)));

Too many parentheses.

...

> +       val |= (BIT(irqd_to_hwirq(d)));

Ditto.

...

> +       /* go through INTx A, B, C, D until all interrupts are handled */
> +       do {
> +               status = iproc_pcie_read_reg(pcie, IPROC_PCIE_INTX_CSR);
> +               for_each_set_bit(bit, &status, PCI_NUM_INTX) {
> +                       virq = irq_find_mapping(pcie->irq_domain, bit);
> +                       if (virq)
> +                               generic_handle_irq(virq);

> +                       else
> +                               dev_err(dev, "unexpected INTx%u\n", bit);

Any guarantee it will be no storm of undesired messages here?

> +               }

> +       } while ((status & SYS_RC_INTX_MASK) != 0);

' != 0' part is not needed.

If there an interrupt storm the handler will never end, right?
Is it the idea by design?

...

> +       node = of_get_compatible_child(dev->of_node, "brcm,iproc-intc");
> +       if (node)
> +               pcie->irq = of_irq_get(node, 0);
> +
> +       if (!node || pcie->irq <= 0)
> +               return 0;

Perhaps
       node = of_get_compatible_child(dev->of_node, "brcm,iproc-intc");
       if (!node)
               return 0;

       pcie->irq = of_irq_get(node, 0);
       if (pcie->irq <= 0)
              return 0;
?

-- 
With Best Regards,
Andy Shevchenko

  parent reply	other threads:[~2020-03-26 14:37 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-26  6:48 [PATCH v5 0/6] PAXB INTx support with proper model Srinath Mannam
2020-03-26  6:48 ` [PATCH v5 1/6] dt-bindings: pci: Update iProc PCI binding for INTx support Srinath Mannam
2020-03-26 12:37   ` Arnd Bergmann
2020-03-26 14:22   ` Bjorn Helgaas
2020-03-26 14:51   ` Marc Zyngier
2020-03-26  6:48 ` [PATCH v5 2/6] PCI: iproc: Add INTx support with better modeling Srinath Mannam
2020-03-26 12:34   ` Arnd Bergmann
2020-03-26 14:37   ` Andy Shevchenko [this message]
2020-03-26 15:03   ` Marc Zyngier
2020-03-26  6:48 ` [PATCH v5 3/6] arm: dts: Change PCIe INTx mapping for Cygnus Srinath Mannam
2020-03-26  6:48 ` [PATCH v5 4/6] arm: dts: Change PCIe INTx mapping for NSP Srinath Mannam
2020-03-26  6:48 ` [PATCH v5 5/6] arm: dts: Change PCIe INTx mapping for HR2 Srinath Mannam
2020-03-26  6:48 ` [PATCH v5 6/6] arm64: dts: Change PCIe INTx mapping for NS2 Srinath Mannam

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