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Mon, 23 May 2022 11:48:10 -0700 (PDT) MIME-Version: 1.0 References: <1646644054-24421-1-git-send-email-hongxing.zhu@nxp.com> <1646644054-24421-6-git-send-email-hongxing.zhu@nxp.com> In-Reply-To: From: Tim Harvey Date: Mon, 23 May 2022 11:47:59 -0700 Message-ID: Subject: Re: [PATCH v2 5/7] arm64: dts: imx8mp: add the iMX8MP PCIe support To: Hongxing Zhu Cc: Lucas Stach , "p.zabel@pengutronix.de" , "bhelgaas@google.com" , "lorenzo.pieralisi@arm.com" , "robh@kernel.org" , "shawnguo@kernel.org" , "vkoul@kernel.org" , "alexander.stein@ew.tq-group.com" , "linux-phy@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "kernel@pengutronix.de" , dl-linux-imx Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sun, Apr 17, 2022 at 10:00 PM Hongxing Zhu wrote: > > > -----Original Message----- > > From: Lucas Stach > > Sent: 2022=E5=B9=B44=E6=9C=8815=E6=97=A5 5:03 > > To: Hongxing Zhu ; p.zabel@pengutronix.de; > > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org; > > shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com > > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > > > > Subject: Re: [PATCH v2 5/7] arm64: dts: imx8mp: add the iMX8MP PCIe > > support > > > > Am Montag, dem 07.03.2022 um 17:07 +0800 schrieb Richard Zhu: > > > Add the i.MX8MP PCIe support. > > > > > > Signed-off-by: Richard Zhu > > > --- > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 > > > ++++++++++++++++++++++- > > > 1 file changed, 45 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > index b40a5646f205..e7b3d8029e34 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > @@ -5,6 +5,7 @@ > > > > > > #include > > > #include > > > +#include > > > #include > > > #include > > > #include > > > @@ -375,7 +376,8 @@ iomuxc: pinctrl@30330000 { > > > }; > > > > > > gpr: iomuxc-gpr@30340000 { > > > - compatible =3D "fsl,imx8mp-iomuxc-gpr", "= syscon"; > > > + compatible =3D "fsl,imx8mp-iomuxc-gpr", > > > + "fsl,imx6q-iomuxc-gpr", "sys= con"; > > > reg =3D <0x30340000 0x10000>; > > > }; > > > > > > @@ -965,6 +967,17 @@ aips4: bus@32c00000 { > > > #size-cells =3D <1>; > > > ranges; > > > > > > + pcie_phy: pcie-phy@32f00000 { > > > + compatible =3D "fsl,imx8mp-pcie-phy"; > > > + reg =3D <0x32f00000 0x10000>; > > > + resets =3D <&src IMX8MP_RESET_PCIEPHY>, > > > + <&src IMX8MP_RESET_PCIEPHY_PERST= >; > > > + reset-names =3D "pciephy", "perst"; > > > + power-domains =3D <&hsio_blk_ctrl > > IMX8MP_HSIOBLK_PD_PCIE_PHY>; > > > + #phy-cells =3D <0>; > > > + status =3D "disabled"; > > > + }; > > > + > > > hsio_blk_ctrl: blk-ctrl@32f10000 { > > > compatible =3D "fsl,imx8mp-hsio-blk-ctrl"= , "syscon"; > > > reg =3D <0x32f10000 0x24>; > > > @@ -980,6 +993,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 { > > > }; > > > }; > > > > > > + pcie: pcie@33800000 { > > > + compatible =3D "fsl,imx8mp-pcie"; > > > + reg =3D <0x33800000 0x400000>, <0x1ff00000 0x8000= 0>; > > > + reg-names =3D "dbi", "config"; > > > + #address-cells =3D <3>; > > > + #size-cells =3D <2>; > > > + device_type =3D "pci"; > > > + bus-range =3D <0x00 0xff>; > > > + ranges =3D <0x81000000 0 0x00000000 0x1ff80000 0 > > 0x00010000 /* downstream I/O 64KB */ > > > + 0x82000000 0 0x18000000 0x18000000 0 > > 0x07f00000>; /* non-prefetchable memory */ > > > + num-lanes =3D <1>; > > > + num-viewport =3D <4>; > > > + interrupts =3D ; > > > + interrupt-names =3D "msi"; > > > + #interrupt-cells =3D <1>; > > > + interrupt-map-mask =3D <0 0 0 0x7>; > > > + interrupt-map =3D <0 0 0 1 &gic GIC_SPI 126 > > IRQ_TYPE_LEVEL_HIGH>, > > > + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYP= E_LEVEL_HIGH>, > > > + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYP= E_LEVEL_HIGH>, > > > + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYP= E_LEVEL_HIGH>; > > > + fsl,max-link-speed =3D <3>; > > > > I believe that imx6_pcie_start_link does not properly handle Gen3 speed= s. > Good caught. > The according link_gen condition should be changed in driver too. > Would be changed in next version. > Thanks. > > Best Regards > Richard Zhu > > > > Regards, > > Lucas > > > > > + linux,pci-domain =3D <0>; > > > + power-domains =3D <&hsio_blk_ctrl IMX8MP_HSIOBLK_= PD_PCIE>; > > > + resets =3D <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, > > > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOF= F>; > > > + reset-names =3D "apps", "turnoff"; > > > + phys =3D <&pcie_phy>; > > > + phy-names =3D "pcie-phy"; > > > + status =3D "disabled"; > > > + }; > > > + > > > gpu3d: gpu@38000000 { > > > compatible =3D "vivante,gc"; > > > reg =3D <0x38000000 0x8000>; > > > Richard, Do you have an updated series for IMX8MP PCIe yet? I believe everything you were waiting on is now merged (blk-ctrl and power-domain). Best Regards, Tim