From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F02D8CA9EC7 for ; Wed, 30 Oct 2019 23:31:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF79420874 for ; Wed, 30 Oct 2019 23:31:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572478318; bh=ElTGOSuLgUTQYq8XexZSn2d5bXU2JaveiSKeV6HCZy8=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=jEe6oz1HGuFUNRd/5iUIO15XPpZeRrrqLqj/B0zyscZ2E25DmIOTGbkDVfGwFbgSY sxfuREj7Ol5WenTiCsZ4teShegLi0k58uv3jkmRnEEIKKX5dLqOBT80PDHlJRPO+Jn gF9HmMmcgB/6Z4fwAMAKUWkIEvyRAHcyFKZlW3uw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726620AbfJ3Xb6 (ORCPT ); Wed, 30 Oct 2019 19:31:58 -0400 Received: from mail-oi1-f193.google.com ([209.85.167.193]:41768 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726273AbfJ3Xb6 (ORCPT ); Wed, 30 Oct 2019 19:31:58 -0400 Received: by mail-oi1-f193.google.com with SMTP id g81so3564757oib.8; Wed, 30 Oct 2019 16:31:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rXx2GYmLM7U7zBzNY7wC7H96LX/I00Fb3y4/X6I00lM=; b=hKByCjWvdYjFKbdtog7rWeR0HGGmf0Jr5yyzP5X7S1WtPL4m6Pgpvn5zydRkSDSm3U R/jqEnwseYIFN/rYz1GVnD4ruIpSvJLyt+sHGu3B1t7NKD41Kq3PgmiHWRgE8LEP5pqQ MixcmOd0ENTgjyL5IyOAZVAtup+t5AjR8Kl0apEApwx5WUAJ+YidobrTQNVC/szvOw4b wkpcEnq/1soPacFxuRwPsz+pUKMwHqp58eDswRRJQmzn4W6dd9eCM0ZJR4mGs583IABE JnRNF0Ub16APJTj+Eg9sLoDlF9RaMER+yFfXIA+/yu9DiP5LU5enms8YxICIWZr+cYU5 0BJQ== X-Gm-Message-State: APjAAAXUpfXOfmcKP/bWNyeRmImEHj8WqXua9zel/dOKmh5Cg5C5/SKa Xs/PMqJcR21GkvS3FP0Nwc8FhGQl8QID/x4Bwio= X-Google-Smtp-Source: APXvYqw845lK8btbYbzWMJIQX20f12jmmkksgbHhAetNT1BSGuSrcZ+htSZfoomUuVAybDhFr7bRJXfzXcMuAzOrof4= X-Received: by 2002:aca:bdc2:: with SMTP id n185mr1535587oif.103.1572478315453; Wed, 30 Oct 2019 16:31:55 -0700 (PDT) MIME-Version: 1.0 References: <20191030221436.GA261632@google.com> In-Reply-To: <20191030221436.GA261632@google.com> From: "Rafael J. Wysocki" Date: Thu, 31 Oct 2019 00:31:44 +0100 Message-ID: Subject: Re: [PATCH v4 3/3] pci: intel: Add sysfs attributes to configure pcie link To: Bjorn Helgaas Cc: Dilip Kota , Andrew Murray , Jingoo Han , gustavo.pimentel@synopsys.com, Lorenzo Pieralisi , Rob Herring , martin.blumenstingl@googlemail.com, Linux PCI , Christoph Hellwig , "devicetree@vger.kernel.org" , Linux Kernel Mailing List , "Shevchenko, Andriy" , cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com, "Rafael J. Wysocki" , Linux PM , Rajat Jain , Heiner Kallweit Content-Type: text/plain; charset="UTF-8" Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, Oct 30, 2019 at 11:14 PM Bjorn Helgaas wrote: > > [+cc Heiner, Rajat] > > On Tue, Oct 29, 2019 at 05:31:18PM +0800, Dilip Kota wrote: > > On 10/22/2019 8:59 PM, Bjorn Helgaas wrote: > > > [+cc Rafael, linux-pm, beginning of discussion at > > > https://lore.kernel.org/r/d8574605f8e70f41ce1e88ccfb56b63c8f85e4df.1571638827.git.eswara.kota@linux.intel.com] > > > > > > On Tue, Oct 22, 2019 at 05:27:38PM +0800, Dilip Kota wrote: > > > > On 10/22/2019 1:18 AM, Bjorn Helgaas wrote: > > > > > On Mon, Oct 21, 2019 at 02:38:50PM +0100, Andrew Murray wrote: > > > > > > On Mon, Oct 21, 2019 at 02:39:20PM +0800, Dilip Kota wrote: > > > > > > > PCIe RC driver on Intel Gateway SoCs have a requirement > > > > > > > of changing link width and speed on the fly. > > > > > Please add more details about why this is needed. Since you're adding > > > > > sysfs files, it sounds like it's not actually the *driver* that needs > > > > > this; it's something in userspace? > > > > We have use cases to change the link speed and width on the fly. > > > > One is EMI check and other is power saving. Some battery backed > > > > applications have to switch PCIe link from higher GEN to GEN1 and > > > > width to x1. During the cases like external power supply got > > > > disconnected or broken. Once external power supply is connected then > > > > switch PCIe link to higher GEN and width. > > > That sounds plausible, but of course nothing there is specific to the > > > Intel Gateway, so we should implement this generically so it would > > > work on all hardware. > > Agree. > > > > > > I'm not sure what the interface should look like -- should it be a > > > low-level interface as you propose where userspace would have to > > > identify each link of interest, or is there some system-wide > > > power/performance knob that could tune all links? Cc'd Rafael and > > > linux-pm in case they have ideas. > > > > To my knowledge sysfs is the appropriate way to go. > > If there are any other best possible knobs, will be helpful. > > I agree sysfs is the right place for it; my question was whether we > should have files like: > > /sys/.../0000:00:1f.3/pcie_speed > /sys/.../0000:00:1f.3/pcie_width > > as I think this patch would add (BTW, please include sample paths like > the above in the commit log), or whether there should be a more global > thing that would affect all the links in the system. > > I think the low-level files like you propose would be better because > one might want to tune link performance differently for different > types of devices and workloads. > > We also have to decide if these files should be associated with the > device at the upstream or downstream end of the link. For ASPM, the > current proposal [1] has the files at the downstream end on the theory > that the GPU, NIC, NVMe device, etc is the user-recognizable one. > Also, neither ASPM nor link speed/width make any sense unless there > *is* a device at the downstream end, so putting them there > automatically makes them visible only when they're useful. > > Rafael had some concerns about the proposed ASPM interface [2], but I > don't know what they are yet. I was talking about the existing ASPM interface in sysfs. The new one I still have to review, but I'm kind of wondering what about people who used the old one? Would it be supported going forward? > For ASPM we added a "link_pm" directory, and maybe that's too > specific. Maybe it should be a generic "link_mgt" or even "pcie" > directory that could contain both the ASPM and width/speed files. > > There's also a change coming to put AER stats in something like this: > > /sys/.../0000:00:1f.3/aer_stats/correctable_rx_err > /sys/.../0000:00:1f.3/aer_stats/correctable_timeout > /sys/.../0000:00:1f.3/aer_stats/fatal_TLP > ... > > It would certainly be good to have some organizational scheme or we'll > end up with a real hodge-podge. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/commit/?h=pci/aspm&id=ad46fe1c733656611788e2cd59793e891ed7ded7 > [2] https://lore.kernel.org/r/CAJZ5v0jdxR4roEUC_Hs3puCzGY4ThdLsi_XcxfBUUxqruP4z7A@mail.gmail.com