From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: MIME-Version: 1.0 References: <1535453838-12154-1-git-send-email-sunil.kovvuri@gmail.com> <1535453838-12154-11-git-send-email-sunil.kovvuri@gmail.com> In-Reply-To: <1535453838-12154-11-git-send-email-sunil.kovvuri@gmail.com> From: Arnd Bergmann Date: Tue, 28 Aug 2018 14:08:55 +0200 Message-ID: Subject: Re: [PATCH 10/15] soc: octeontx2: Reconfig MSIX base with IOVA To: sunil.kovvuri@gmail.com List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , Marc Zyngier , linux-pci , Linux Kernel Mailing List , Linux ARM , Olof Johansson , Thomas Gleixner , linux-soc@vger.kernel.org, gakula@marvell.com, sgoutham@marvell.com Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: On Tue, Aug 28, 2018 at 12:58 PM wrote: > > From: Geetha sowjanya > > HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence > create a IOMMU mapping for the physcial address configured by > firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA. > > Signed-off-by: Geetha sowjanya > Signed-off-by: Sunil Goutham I think this needs some more explanation. What is the difference between the MSI-X support in this driver and every other one? Are you working around a hardware bug, or is there something odd in the implementation of your irqchip driver? Do you use a GIC to handle the MSI interrupts or something else? Arnd _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel