Linux-PCI Archive on lore.kernel.org
 help / color / Atom feed
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Will Deacon <will.deacon@arm.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	linux-pci <linux-pci@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Marcin Wojtas <mw@semihalf.com>,
	Leif Lindholm <leif.lindholm@linaro.org>,
	Graeme Gregory <graeme.gregory@linaro.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v3 1/2] pci: designware: add driver for DWC controller in ECAM shift mode
Date: Thu, 28 Sep 2017 09:04:09 -0700
Message-ID: <CAKv+Gu-rSUVEufN71uazdTz443PLJDw56jMKxo=y8xYV-5ziZw@mail.gmail.com> (raw)
In-Reply-To: <20170928160019.GC9892@arm.com>

On 28 September 2017 at 09:00, Will Deacon <will.deacon@arm.com> wrote:
> On Thu, Sep 28, 2017 at 08:57:28AM -0700, Ard Biesheuvel wrote:
>> On 28 September 2017 at 02:03, Will Deacon <will.deacon@arm.com> wrote:
>> > On Tue, Sep 26, 2017 at 12:32:00PM -0500, Bjorn Helgaas wrote:
>> >> [+cc Will]
>> >>
>> >> On Mon, Aug 28, 2017 at 07:04:36PM +0100, Ard Biesheuvel wrote:
>> >> > Some implementations of the Synopsys Designware PCIe controller implement
>> >> > a so-called ECAM shift mode, which allows a static memory window to be
>> >> > configured that covers the configuration space of the entire bus range.
>> >> >
>> >> > If the firmware performs all the low level configuration that is required
>> >> > to expose this controller in a fully ECAM compatible manner, we can
>> >> > simply describe it as "pci-host-ecam-generic" and be done with it.
>> >> > However, it appears that in some cases (one of which is the Armada 80x0),
>> >> > the IP is synthesized with an ATU window size that does not allow the
>> >> > first bus to be mapped in a way that prevents the device on the
>> >> > downstream port from appearing more than once.
>> >> >
>> >> > So implement a driver that relies on the firmware to perform all low
>> >> > level initialization, and drives the controller in ECAM mode, but
>> >> > overrides the config space accessors to take the above quirk into
>> >> > account.
>> >> >
>> >> > Note that, unlike most drivers for this IP, this driver does not expose
>> >> > a fake bridge device at B/D/F 00:00.0. There is no point in doing so,
>> >> > given that this is not a true bridge, and does not require any windows
>> >> > to be configured in order for the downstream device to operate correctly.
>> >> > Omitting it also prevents the PCI resource allocation routines from
>> >> > handing out BAR space to it unnecessarily.
>> >>
>> >> This is a tangent, but does this mean the other drivers do not need to
>> >> expose a fake 00:00.0 device either?
>> >>
>> >> s/Designware/DesignWare/ in comments, changelogs, Kconfig text, etc.
>> >>
>> >> > Cc: Bjorn Helgaas <bhelgaas@google.com>
>> >> > Cc: Jingoo Han <jingoohan1@gmail.com>
>> >> > Cc: Joao Pinto <Joao.Pinto@synopsys.com>
>> >> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> >> > ---
>> >> >  drivers/pci/dwc/Kconfig                | 11 +++
>> >> >  drivers/pci/dwc/Makefile               |  1 +
>> >> >  drivers/pci/dwc/pcie-designware-ecam.c | 77 ++++++++++++++++++++
>> >>
>> >> This really doesn't have any DesignWare specifics in it, and it seems
>> >> more related to drivers/pci/host/pci-host-generic.c than to anything
>> >> in drivers/pci/dwc.  Maybe it should be
>> >> drivers/pci/host/pci-host-generic-quirks.c or something?  That's
>> >> unwieldy, I admit.
>> >>
>> >> Putting it in pci/dwc would make Jingoo and Joao the default
>> >> maintainers; I don't know how they feel about that.  We would probably
>> >> have to tweak MAINTAINERS if we *didn't* put it in pci/dwc.
>> >>
>> >> Any thoughts on this, Will?
>> >
>> > The idea of a "generic quirk" makes me smile, I must admit :)
>> >
>> > I think there are two options:
>> >
>> >   1. Use the full DWC driver, and don't rely on firmware
>> > -or-
>> >   2. Rely on firmware, but teach pci-host-generic to deal with the funny
>> >      config space
>> >
>> > For (2), we probably want to describe this as generically as possible
>> > in case some other SoCs run into the same problem.
>> >
>>
>> I take it this implies a DT property. I could add one that consists of
>> an array of val/mask tuples or base/size tuples that allow us to
>> disable arbitrary subregions of the config space. I could also add a
>> simple boolean property that implements this exact quirk. Do you have
>> any preference?
>
> I'd say either a boolean property or a new compatible string. I think Rob
> prefers the latter, from what he said recently on an SMMU thread.
>

OK. Given that Rob already acked the binding for this driver, I'll go
ahead and rework the patch to add

+       { .compatible = "marvell,armada8k-pcie-ecam" },
+       { .compatible = "socionext,synquacer-pcie-ecam" },
+       { .compatible = "snps,dw-pcie-ecam" },

to the pci-host-ecam-generic driver instead.

Thanks,
Ard.

  reply index

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-28 18:04 [PATCH v3 0/2] pci: add support for firmware initialized designware RCs Ard Biesheuvel
2017-08-28 18:04 ` [PATCH v3 1/2] pci: designware: add driver for DWC controller in ECAM shift mode Ard Biesheuvel
2017-09-26 17:32   ` Bjorn Helgaas
2017-09-28  9:03     ` Will Deacon
2017-09-28 15:57       ` Ard Biesheuvel
2017-09-28 16:00         ` Will Deacon
2017-09-28 16:04           ` Ard Biesheuvel [this message]
2017-09-28 15:51     ` Ard Biesheuvel
2017-09-28 17:48       ` Bjorn Helgaas
2017-09-28 18:33         ` Ard Biesheuvel
2017-09-29  3:29         ` Jingoo Han
2017-10-06 14:52       ` Ard Biesheuvel
2017-10-06 22:45         ` Bjorn Helgaas
2017-10-06 23:10           ` Ard Biesheuvel
2017-08-28 18:04 ` [PATCH v3 2/2] dt-bindings: designware: add binding for Designware PCIe in ECAM mode Ard Biesheuvel
2017-08-31 14:23   ` Rob Herring
2017-08-29 15:40 ` [PATCH v3 0/2] pci: add support for firmware initialized designware RCs Marcin Wojtas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAKv+Gu-rSUVEufN71uazdTz443PLJDw56jMKxo=y8xYV-5ziZw@mail.gmail.com' \
    --to=ard.biesheuvel@linaro.org \
    --cc=Joao.Pinto@synopsys.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=graeme.gregory@linaro.org \
    --cc=helgaas@kernel.org \
    --cc=jingoohan1@gmail.com \
    --cc=leif.lindholm@linaro.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=mw@semihalf.com \
    --cc=robh@kernel.org \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Linux-PCI Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \
		linux-pci@vger.kernel.org
	public-inbox-index linux-pci

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git