From: Rob Herring <robh@kernel.org>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Andrew Murray <amurray@thegoodpenguin.co.uk>,
Thierry Reding <treding@nvidia.com>,
Jon Hunter <jonathanh@nvidia.com>,
PCI <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
kthota@nvidia.com, Manikanta Maddireddy <mmaddireddy@nvidia.com>,
sagar.tv@gmail.com
Subject: Re: [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC
Date: Mon, 2 Nov 2020 08:15:47 -0600 [thread overview]
Message-ID: <CAL_Jsq+3Ek9SRbsTqEmjiZtszvi7Er=TNgOt8t=0OESva2=sTg@mail.gmail.com> (raw)
In-Reply-To: <20201029053959.31361-3-vidyas@nvidia.com>
On Thu, Oct 29, 2020 at 12:40 AM Vidya Sagar <vidyas@nvidia.com> wrote:
>
> DesignWare core has a TLP digest (TD) override bit in one of the control
> registers of ATU. This bit also needs to be programmed for proper ECRC
> functionality. This is currently identified as an issue with DesignWare
> IP version 4.90a. This patch does the required programming in ATU upon
> querying the system policy for ECRC.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
> ---
> V3:
> * Added 'Reviewed-by: Jingoo Han <jingoohan1@gmail.com>'
>
> V2:
> * Addressed Jingoo's review comment
> * Removed saving 'td' bit information in 'dw_pcie' structure
>
> drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index b5e438b70cd5..cbd651b219d2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -246,6 +246,8 @@ static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
> dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
> upper_32_bits(pci_addr));
> val = type | PCIE_ATU_FUNC_NUM(func_no);
> + if (pci->version == 0x490A)
> + val = val | pcie_is_ecrc_enabled() << PCIE_ATU_TD_SHIFT;
> val = upper_32_bits(size - 1) ?
> val | PCIE_ATU_INCREASE_REGION_SIZE : val;
> dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val);
> @@ -294,8 +296,10 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
> lower_32_bits(pci_addr));
> dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
> upper_32_bits(pci_addr));
> - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> - PCIE_ATU_FUNC_NUM(func_no));
> + val = type | PCIE_ATU_FUNC_NUM(func_no);
> + if (pci->version == 0x490A)
Is this even possible? Are the non-unroll ATU registers available post 4.80?
Rob
next prev parent reply other threads:[~2020-11-02 14:18 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-29 5:39 [PATCH V3 0/2] Add support to configure DWC for ECRC Vidya Sagar
2020-10-29 5:39 ` [PATCH V3 1/2] PCI/AER: Add pcie_is_ecrc_enabled() API Vidya Sagar
2020-10-29 5:39 ` [PATCH V3 2/2] PCI: dwc: Add support to configure for ECRC Vidya Sagar
2020-10-29 22:03 ` Jingoo Han
2020-10-30 6:45 ` Vidya Sagar
2020-11-02 14:15 ` Rob Herring [this message]
2020-11-02 14:27 ` Vidya Sagar
2020-11-02 15:11 ` Gustavo Pimentel
2020-11-02 21:16 ` Rob Herring
2020-11-02 22:38 ` Gustavo Pimentel
2020-11-03 19:48 ` Rob Herring
2020-11-02 23:02 ` Bjorn Helgaas
2020-11-03 3:27 ` Vidya Sagar
2020-11-03 21:07 ` Bjorn Helgaas
2020-11-04 11:43 ` Vidya Sagar
2020-11-04 16:22 ` Bjorn Helgaas
2020-11-04 17:40 ` Vidya Sagar
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