Linux-PCI Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
@ 2020-10-26 15:48 Rob Herring
  2020-10-26 16:22 ` Jingoo Han
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Rob Herring @ 2020-10-26 15:48 UTC (permalink / raw)
  To: linux-pci
  Cc: Vidya Sagar, Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi,
	Bjorn Helgaas

Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
resources"), the DWC driver was setting up the last memory resource
rather than the first memory resource. This doesn't matter for most
platforms which only have 1 memory resource, but it broke Tegra194 which
has a 2nd (prefetchable) memory region which requires an ATU entry. The
first region on Tegra194 relies on the default 1:1 pass-thru of outbound
transactions which doesn't need an ATU entry.

Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
Reported-by: Vidya Sagar <vidyas@nvidia.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 674f32db85ca..44c2a6572199 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	 * ATU, so we should not program the ATU here.
 	 */
 	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
-		struct resource_entry *entry =
-			resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
+		struct resource_entry *tmp, *entry = NULL;
+
+		/* Get last memory resource entry */
+		resource_list_for_each_entry(tmp, &pp->bridge->windows)
+			if (resource_type(tmp->res) == IORESOURCE_MEM)
+				entry = tmp;
 
 		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
 					  PCIE_ATU_TYPE_MEM, entry->res->start,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
  2020-10-26 15:48 [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry Rob Herring
@ 2020-10-26 16:22 ` Jingoo Han
  2020-10-26 16:49 ` Vidya Sagar
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 6+ messages in thread
From: Jingoo Han @ 2020-10-26 16:22 UTC (permalink / raw)
  To: Rob Herring, linux-pci
  Cc: Vidya Sagar, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas,
	Han Jingoo

On 10/26/20, 11:48 AM, Rob Herring wrote:
> 
> Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
> resources"), the DWC driver was setting up the last memory resource
> rather than the first memory resource. This doesn't matter for most
> platforms which only have 1 memory resource, but it broke Tegra194 which
> has a 2nd (prefetchable) memory region which requires an ATU entry. The
> first region on Tegra194 relies on the default 1:1 pass-thru of outbound
> transactions which doesn't need an ATU entry.
>
> Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
> Reported-by: Vidya Sagar <vidyas@nvidia.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 674f32db85ca..44c2a6572199 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	 * ATU, so we should not program the ATU here.
>  	 */
>  	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> -		struct resource_entry *entry =
> -			resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> +		struct resource_entry *tmp, *entry = NULL;
> +
> +		/* Get last memory resource entry */
> +		resource_list_for_each_entry(tmp, &pp->bridge->windows)
> +			if (resource_type(tmp->res) == IORESOURCE_MEM)
> +				entry = tmp;
>
>  		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
>  					  PCIE_ATU_TYPE_MEM, entry->res->start,
> -- 
> 2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
  2020-10-26 15:48 [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry Rob Herring
  2020-10-26 16:22 ` Jingoo Han
@ 2020-10-26 16:49 ` Vidya Sagar
  2020-10-26 18:02   ` Rob Herring
  2020-11-03 16:24 ` Lorenzo Pieralisi
  2020-11-03 19:30 ` Bjorn Helgaas
  3 siblings, 1 reply; 6+ messages in thread
From: Vidya Sagar @ 2020-10-26 16:49 UTC (permalink / raw)
  To: Rob Herring, linux-pci
  Cc: Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas



On 10/26/2020 9:18 PM, Rob Herring wrote:
> External email: Use caution opening links or attachments
> 
> 
> Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
> resources"), the DWC driver was setting up the last memory resource
> rather than the first memory resource. This doesn't matter for most
> platforms which only have 1 memory resource, but it broke Tegra194 which
> has a 2nd (prefetchable) memory region which requires an ATU entry. The
> first region on Tegra194 relies on the default 1:1 pass-thru of outbound
> transactions which doesn't need an ATU entry.
> 
> Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
> Reported-by: Vidya Sagar <vidyas@nvidia.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>   drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
>   1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 674f32db85ca..44c2a6572199 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>           * ATU, so we should not program the ATU here.
>           */
>          if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> -               struct resource_entry *entry =
> -                       resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> +               struct resource_entry *tmp, *entry = NULL;
> +
> +               /* Get last memory resource entry */
> +               resource_list_for_each_entry(tmp, &pp->bridge->windows)
> +                       if (resource_type(tmp->res) == IORESOURCE_MEM)
> +                               entry = tmp;
This patch works for Tegra194 with its 'ranges' property in its current 
shape. But, this still doesn't work if ATU mapping needs to be set for 
both prefetchable and non-prefetchable regions. The series I pushed at 
http://patchwork.ozlabs.org/project/linux-pci/list/?series=209764 works 
for this condition as well.
When it comes to configuring the ATU to handle multiple memory apertures 
(which is the ultimate goal), I think we need to understand the side 
effects of removing I/O mapping in platforms where the number of view 
ports available are not enough to have I/O mapping.

> 
>                  dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
>                                            PCIE_ATU_TYPE_MEM, entry->res->start,
> --
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
  2020-10-26 16:49 ` Vidya Sagar
@ 2020-10-26 18:02   ` Rob Herring
  0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2020-10-26 18:02 UTC (permalink / raw)
  To: Vidya Sagar
  Cc: PCI, Jingoo Han, Gustavo Pimentel, Lorenzo Pieralisi, Bjorn Helgaas

On Mon, Oct 26, 2020 at 11:49 AM Vidya Sagar <vidyas@nvidia.com> wrote:
>
>
>
> On 10/26/2020 9:18 PM, Rob Herring wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
> > resources"), the DWC driver was setting up the last memory resource
> > rather than the first memory resource. This doesn't matter for most
> > platforms which only have 1 memory resource, but it broke Tegra194 which
> > has a 2nd (prefetchable) memory region which requires an ATU entry. The
> > first region on Tegra194 relies on the default 1:1 pass-thru of outbound
> > transactions which doesn't need an ATU entry.
> >
> > Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
> > Reported-by: Vidya Sagar <vidyas@nvidia.com>
> > Cc: Jingoo Han <jingoohan1@gmail.com>
> > Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > ---
> >   drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
> >   1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> > index 674f32db85ca..44c2a6572199 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> > @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> >           * ATU, so we should not program the ATU here.
> >           */
> >          if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> > -               struct resource_entry *entry =
> > -                       resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> > +               struct resource_entry *tmp, *entry = NULL;
> > +
> > +               /* Get last memory resource entry */
> > +               resource_list_for_each_entry(tmp, &pp->bridge->windows)
> > +                       if (resource_type(tmp->res) == IORESOURCE_MEM)
> > +                               entry = tmp;
> This patch works for Tegra194 with its 'ranges' property in its current
> shape. But, this still doesn't work if ATU mapping needs to be set for
> both prefetchable and non-prefetchable regions.

Supporting both is not a current feature and therefore not 5.10
material. This patch is intended for 5.10. Adding support for multiple
memory regions would be 5.11 material.

> The series I pushed at
> http://patchwork.ozlabs.org/project/linux-pci/list/?series=209764 works
> for this condition as well.

I have an alternative implementation that I'll send out shortly.

> When it comes to configuring the ATU to handle multiple memory apertures
> (which is the ultimate goal), I think we need to understand the side
> effects of removing I/O mapping in platforms where the number of view
> ports available are not enough to have I/O mapping.

We don't have that case upstream AFAICT. Tegra is the only platform
with more than 1 memory region which could cause a change in behavior.
In any case, I'm not removing the sharing of ATU for config and i/o
(though I think we should). I am adding a warning though.

Rob

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
  2020-10-26 15:48 [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry Rob Herring
  2020-10-26 16:22 ` Jingoo Han
  2020-10-26 16:49 ` Vidya Sagar
@ 2020-11-03 16:24 ` Lorenzo Pieralisi
  2020-11-03 19:30 ` Bjorn Helgaas
  3 siblings, 0 replies; 6+ messages in thread
From: Lorenzo Pieralisi @ 2020-11-03 16:24 UTC (permalink / raw)
  To: Rob Herring, Bjorn Helgaas
  Cc: linux-pci, Vidya Sagar, Jingoo Han, Gustavo Pimentel

On Mon, Oct 26, 2020 at 10:48:52AM -0500, Rob Herring wrote:
> Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
> resources"), the DWC driver was setting up the last memory resource
> rather than the first memory resource. This doesn't matter for most
> platforms which only have 1 memory resource, but it broke Tegra194 which
> has a 2nd (prefetchable) memory region which requires an ATU entry. The
> first region on Tegra194 relies on the default 1:1 pass-thru of outbound
> transactions which doesn't need an ATU entry.
> 
> Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
> Reported-by: Vidya Sagar <vidyas@nvidia.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)

Bjorn, this is v5.10 material please pick it up for one of the
upcoming -rc*:

Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>

> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 674f32db85ca..44c2a6572199 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	 * ATU, so we should not program the ATU here.
>  	 */
>  	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> -		struct resource_entry *entry =
> -			resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> +		struct resource_entry *tmp, *entry = NULL;
> +
> +		/* Get last memory resource entry */
> +		resource_list_for_each_entry(tmp, &pp->bridge->windows)
> +			if (resource_type(tmp->res) == IORESOURCE_MEM)
> +				entry = tmp;
>  
>  		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
>  					  PCIE_ATU_TYPE_MEM, entry->res->start,
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
  2020-10-26 15:48 [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry Rob Herring
                   ` (2 preceding siblings ...)
  2020-11-03 16:24 ` Lorenzo Pieralisi
@ 2020-11-03 19:30 ` Bjorn Helgaas
  3 siblings, 0 replies; 6+ messages in thread
From: Bjorn Helgaas @ 2020-11-03 19:30 UTC (permalink / raw)
  To: Rob Herring
  Cc: linux-pci, Vidya Sagar, Jingoo Han, Gustavo Pimentel,
	Lorenzo Pieralisi, Bjorn Helgaas

On Mon, Oct 26, 2020 at 10:48:52AM -0500, Rob Herring wrote:
> Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
> resources"), the DWC driver was setting up the last memory resource
> rather than the first memory resource. This doesn't matter for most
> platforms which only have 1 memory resource, but it broke Tegra194 which
> has a 2nd (prefetchable) memory region which requires an ATU entry. The
> first region on Tegra194 relies on the default 1:1 pass-thru of outbound
> transactions which doesn't need an ATU entry.
> 
> Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
> Reported-by: Vidya Sagar <vidyas@nvidia.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>

Applied with acks from Lorenzo and Jingoo to for-linus for v5.10,
thanks!

> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 674f32db85ca..44c2a6572199 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	 * ATU, so we should not program the ATU here.
>  	 */
>  	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> -		struct resource_entry *entry =
> -			resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> +		struct resource_entry *tmp, *entry = NULL;
> +
> +		/* Get last memory resource entry */
> +		resource_list_for_each_entry(tmp, &pp->bridge->windows)
> +			if (resource_type(tmp->res) == IORESOURCE_MEM)
> +				entry = tmp;
>  
>  		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
>  					  PCIE_ATU_TYPE_MEM, entry->res->start,
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, back to index

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-26 15:48 [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry Rob Herring
2020-10-26 16:22 ` Jingoo Han
2020-10-26 16:49 ` Vidya Sagar
2020-10-26 18:02   ` Rob Herring
2020-11-03 16:24 ` Lorenzo Pieralisi
2020-11-03 19:30 ` Bjorn Helgaas

Linux-PCI Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-pci/0 linux-pci/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-pci linux-pci/ https://lore.kernel.org/linux-pci \
		linux-pci@vger.kernel.org
	public-inbox-index linux-pci

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-pci


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git