From: Rob Herring <robh@kernel.org>
To: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Cc: "Bjorn Helgaas" <helgaas@kernel.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
Linuxarm <linuxarm@huawei.com>,
mauro.chehab@huawei.com, "Krzysztof Wilczyński" <kw@linux.com>,
"Binghui Wang" <wangbinghui@hisilicon.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Xiaowei Song" <songxiaowei@hisilicon.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
PCI <linux-pci@vger.kernel.org>,
"Kishon Vijay Abraham I" <kishon@ti.com>
Subject: Re: [PATCH v15 04/13] PCI: kirin: Add support for bridge slot DT schema
Date: Thu, 4 Nov 2021 10:36:52 -0500 [thread overview]
Message-ID: <CAL_Jsq+qyf=2dSgaVKGPccNGNYXbeyKMDC_yB=G8wg0_4_06Gw@mail.gmail.com> (raw)
In-Reply-To: <20211102174415.58cd3d4f@sal.lan>
On Tue, Nov 2, 2021 at 12:44 PM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Hi Bjorn,
>
> Em Tue, 2 Nov 2021 11:06:12 -0500
> Bjorn Helgaas <helgaas@kernel.org> escreveu:
>
> > > +
> > > + /* Per-slot clkreq */
> > > + int n_gpio_clkreq;
> > > + int gpio_id_clkreq[MAX_PCI_SLOTS];
> > > + const char *clkreq_names[MAX_PCI_SLOTS];
> >
> > I think there's been previous discussion about this, but I didn't
> > follow it, so I'm just double-checking that this is what we want here.
> >
> > IIUC, this (MAX_PCI_SLOTS, "hisilicon,clken-gpios") applies to an
> > external PEX 8606 bridge, which seems a little strange to be
> > hard-coded into the kirin driver this way.
> >
> > I see that "hisilicon,clken-gpios" is optional, but what if some
> > platform connects all 6 lanes? What if there's a different bridge
> > altogether?
Keep in mind this is HiKey. There's never been a 2nd board upstream
for the SoCs, the boards have a short lifespan in terms of both
support and availability. And yet Hikey manages to do multiple
complicated things on the board design. I have a hard time caring...
> >
> > I'll assume this is actually the way we want thing unless I hear
> > otherwise.
>
> Yes, there was past discussions about that with Rob, with regards
> to how the DT would represent it, which got reflected at the code.
At first I thought these were CLKREQ connections which absolutely
should be per port/bridge like PERST, but they are not. They are
simply enables for the refclk's and pretty specific to HiKey.
> At the end, it was decided to just add a single property inside PCIe:
>
>
> pcie@f4000000 {
> compatible = "hisilicon,kirin970-pcie";
> ...
> hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>,
> <&gpio20 6 0>;
>
> I don't think this is a problem, as, if some day another bridge would
> need a larger number of slots, it is just a matter of changing the
> number at the MAX_PCI_SLOTS, as this controls only the size of the array
> (and the check for array overflow when parsing the properties).
It is a problem that your host bridge driver has hardcoded board
specifics. That's not the first time you've heard that from me. But
given the board-to-soc ratio of Hikey is 1:1, I don't care that much.
Rob
next prev parent reply other threads:[~2021-11-04 15:37 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 10:45 [PATCH v15 00/13] Add support for Hikey 970 PCIe Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 01/13] PCI: kirin: Reorganize the PHY logic inside the driver Mauro Carvalho Chehab
2021-11-04 21:48 ` Bjorn Helgaas
2021-10-21 10:45 ` [PATCH v15 02/13] PCI: kirin: Add support for a PHY layer Mauro Carvalho Chehab
2021-10-25 8:14 ` Kishon Vijay Abraham I
2021-10-25 8:52 ` Mauro Carvalho Chehab
2021-10-25 8:56 ` Kishon Vijay Abraham I
2021-10-21 10:45 ` [PATCH v15 03/13] PCI: kirin: Use regmap for APB registers Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 04/13] PCI: kirin: Add support for bridge slot DT schema Mauro Carvalho Chehab
2021-11-02 16:06 ` Bjorn Helgaas
2021-11-02 17:44 ` Mauro Carvalho Chehab
2021-11-02 22:08 ` Pali Rohár
2021-11-04 15:36 ` Rob Herring [this message]
2021-11-04 17:27 ` Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 05/13] PCI: kirin: Give more time for PERST# reset to finish Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 06/13] PCI: kirin: Add Kirin 970 compatible Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 07/13] PCI: kirin: Add MODULE_* macros Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 08/13] PCI: kirin: Allow building it as a module Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 09/13] PCI: kirin: Add power_off support for Kirin 960 PHY Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 10/13] PCI: kirin: Move the power-off code to a common routine Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 11/13] PCI: kirin: Disable clkreq during poweroff sequence Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 12/13] PCI: kirin: De-init the dwc driver Mauro Carvalho Chehab
2021-10-21 10:45 ` [PATCH v15 13/13] PCI: kirin: Allow removing the driver Mauro Carvalho Chehab
2021-10-31 20:55 ` Pali Rohár
2021-10-21 12:17 ` [PATCH v15 00/13] Add support for Hikey 970 PCIe Lorenzo Pieralisi
2021-10-26 17:17 ` Lorenzo Pieralisi
2021-10-27 7:24 ` Mauro Carvalho Chehab
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