From: Rob Herring <robh@kernel.org>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
<linux-pci@vger.kernel.org>,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Christoph Hellwig <hch@lst.de>,
Robin Murphy <robin.murphy@arm.com>,
"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@broadcom.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v11 04/11] PCI: brcmstb: Add suspend and resume pm_ops
Date: Thu, 10 Sep 2020 12:50:34 -0600 [thread overview]
Message-ID: <CAL_JsqJR4wALnsFKKPQ8h2y-o-933rzxHbV29zGXiptgYuuHTg@mail.gmail.com> (raw)
In-Reply-To: <CA+-6iNy9g8fhJvd7SOKtc-SZcL8_gLLN1HEs-W8fe-=q6n430A@mail.gmail.com>
On Thu, Sep 10, 2020 at 10:42 AM Jim Quinlan <james.quinlan@broadcom.com> wrote:
>
> On Thu, Sep 10, 2020 at 11:56 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Mon, Aug 24, 2020 at 03:30:17PM -0400, Jim Quinlan wrote:
> > > From: Jim Quinlan <jquinlan@broadcom.com>
> > >
> > > Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend
> > > and resume. Now the PCIe driver may do so as well.
> > >
> > > Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> > > Acked-by: Florian Fainelli <f.fainelli@gmail.com>
> > > ---
> > > drivers/pci/controller/pcie-brcmstb.c | 47 +++++++++++++++++++++++++++
> > > 1 file changed, 47 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> > > index c2b3d2946a36..3d588ab7a6dd 100644
> > > --- a/drivers/pci/controller/pcie-brcmstb.c
> > > +++ b/drivers/pci/controller/pcie-brcmstb.c
> > > @@ -978,6 +978,47 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
> > > brcm_pcie_bridge_sw_init_set(pcie, 1);
> > > }
> > >
> > > +static int brcm_pcie_suspend(struct device *dev)
> > > +{
> > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > +
> > > + brcm_pcie_turn_off(pcie);
> > > + clk_disable_unprepare(pcie->clk);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int brcm_pcie_resume(struct device *dev)
> > > +{
> > > + struct brcm_pcie *pcie = dev_get_drvdata(dev);
> > > + void __iomem *base;
> > > + u32 tmp;
> > > + int ret;
> > > +
> > > + base = pcie->base;
> > > + clk_prepare_enable(pcie->clk);
> > > +
> > > + /* Take bridge out of reset so we can access the SERDES reg */
> > > + brcm_pcie_bridge_sw_init_set(pcie, 0);
> > > +
> > > + /* SERDES_IDDQ = 0 */
> > > + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> > > + u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
> > > + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> > > +
> > > + /* wait for serdes to be stable */
> > > + udelay(100);
> >
> > Really needs to be a spinloop?
> >
> > > +
> > > + ret = brcm_pcie_setup(pcie);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + if (pcie->msi)
> > > + brcm_msi_set_regs(pcie->msi);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static void __brcm_pcie_remove(struct brcm_pcie *pcie)
> > > {
> > > brcm_msi_remove(pcie);
> > > @@ -1087,12 +1128,18 @@ static int brcm_pcie_probe(struct platform_device *pdev)
> > >
> > > MODULE_DEVICE_TABLE(of, brcm_pcie_match);
> > >
> > > +static const struct dev_pm_ops brcm_pcie_pm_ops = {
> > > + .suspend_noirq = brcm_pcie_suspend,
> > > + .resume_noirq = brcm_pcie_resume,
> >
> > Why do you need interrupts disabled? There's 39 cases of .suspend_noirq
> > and 1352 of .suspend in the tree.
>
> I will test switching this to suspend_late/resume_early.
Why not just the 'regular' flavor suspend/resume?
Rob
next prev parent reply other threads:[~2020-09-10 18:51 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-24 19:30 [PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan
2020-08-24 19:30 ` [PATCH v11 01/11] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan
2020-08-24 19:30 ` [PATCH v11 02/11] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan
2020-08-24 19:30 ` [PATCH v11 03/11] PCI: brcmstb: Add bcm7278 register info Jim Quinlan
2020-09-10 15:44 ` Rob Herring
2020-08-24 19:30 ` [PATCH v11 04/11] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan
2020-09-10 15:56 ` Rob Herring
2020-09-10 16:42 ` Jim Quinlan
2020-09-10 18:50 ` Rob Herring [this message]
2020-09-10 18:54 ` Florian Fainelli
2020-09-10 19:05 ` Jim Quinlan
2020-09-10 19:07 ` Florian Fainelli
2020-09-10 19:09 ` Jim Quinlan
2020-09-10 18:47 ` Florian Fainelli
2020-08-24 19:30 ` [PATCH v11 05/11] PCI: brcmstb: Add bcm7278 PERST# support Jim Quinlan
2020-09-10 16:04 ` Rob Herring
2020-08-24 19:30 ` [PATCH v11 06/11] PCI: brcmstb: Add control of rescal reset Jim Quinlan
2020-09-08 13:32 ` Lorenzo Pieralisi
2020-09-10 16:09 ` Rob Herring
2020-08-24 19:30 ` [PATCH v11 08/11] PCI: brcmstb: Set additional internal memory DMA viewport sizes Jim Quinlan
2020-09-10 16:17 ` Rob Herring
2020-09-11 15:28 ` Jim Quinlan
2020-09-11 16:13 ` Rob Herring
2020-08-24 19:30 ` [PATCH v11 09/11] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan
2020-09-10 16:20 ` Rob Herring
2020-08-24 19:30 ` [PATCH v11 10/11] PCI: brcmstb: Set bus max burst size by chip type Jim Quinlan
2020-09-10 16:22 ` Rob Herring
2020-08-24 19:30 ` [PATCH v11 11/11] PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list Jim Quinlan
2020-09-10 16:23 ` Rob Herring
2020-08-25 17:40 ` [PATCH v11 00/11] PCI: brcmstb: enable PCIe for STB chips Florian Fainelli
2020-08-27 6:35 ` Christoph Hellwig
2020-08-27 13:29 ` Jim Quinlan
2020-09-07 9:16 ` Lorenzo Pieralisi
2020-09-07 17:43 ` Jim Quinlan
2020-09-07 18:29 ` Florian Fainelli
2020-09-08 10:42 ` Lorenzo Pieralisi
2020-09-08 12:20 ` Christoph Hellwig
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