From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B2E7C4332F for ; Tue, 14 Sep 2021 14:04:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0C74F6108B for ; Tue, 14 Sep 2021 14:04:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233464AbhINOFz (ORCPT ); Tue, 14 Sep 2021 10:05:55 -0400 Received: from mail.kernel.org ([198.145.29.99]:41830 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233438AbhINOFz (ORCPT ); Tue, 14 Sep 2021 10:05:55 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 48B5D6109E; Tue, 14 Sep 2021 14:04:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1631628277; bh=iQJMVWDJXIz4+Xnw+Zmg2wTPTmdj6J/jGV1015/5YnY=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=sh0LzS3sjwfoLX0GTTG4bYX4blk6Ke37ZobsjjU36s3FXmpuukuAVFMlrgFE8TZhx EeJTMn0gyT3HSSR4sdkvIe7StpiDB7V85s8j29p5SpXCMfl73qNxySVT8Ie60y2vcV vpix8KeCPPe3P81A+ergZLI6GmhIf4aMDBVK6jpzZa3jwvCpze4fyg8qmaNhURy5Wf aiHr6ir8zwQlRN1fT/mqpLFTqaLxoP/fDxYZ5qICbI5RjU8kbA9HYnpJsD8/cwosjB jIfwjYdhrAcZvCqucxW3WWay2IaphC8JawlfMJP8AiOGLWbBeG+Fw3+RZR7Y1aDhJR 6oIELkkIGQ5Hw== Received: by mail-ed1-f47.google.com with SMTP id t6so18690146edi.9; Tue, 14 Sep 2021 07:04:37 -0700 (PDT) X-Gm-Message-State: AOAM5310p/B6mj6bG67L2XaY/HsdqnmaocVzCvDZ9IrnxLOBCdONFl0S W+sFC8mrsvUTDXFH5XlItBwpJl6xlzk4xm2Wbw== X-Google-Smtp-Source: ABdhPJwUbUy1IP1vgkqhQdfLkWfsy/Qq1h3BMnp5iQMqPnzVJ11nLcXtGK+gUd4ZWnMAlXCfmg09DjEmu8QfDA/aRZs= X-Received: by 2002:a05:6402:b23:: with SMTP id bo3mr16054495edb.145.1631628275923; Tue, 14 Sep 2021 07:04:35 -0700 (PDT) MIME-Version: 1.0 References: <20210722121242.47838-1-manivannan.sadhasivam@linaro.org> <20210722121242.47838-3-manivannan.sadhasivam@linaro.org> In-Reply-To: <20210722121242.47838-3-manivannan.sadhasivam@linaro.org> From: Rob Herring Date: Tue, 14 Sep 2021 09:04:24 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v7 2/3] PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver To: Manivannan Sadhasivam Cc: Kishon Vijay Abraham I , Lorenzo Pieralisi , Bjorn Helgaas , devicetree@vger.kernel.org, PCI , "linux-kernel@vger.kernel.org" , linux-arm-msm , hemantk@codeaurora.org, Siddartha Mohanadoss , Bjorn Andersson , Sriharsha Allenki , skananth@codeaurora.org, vpernami@codeaurora.org, Veerabhadrarao Badiganti Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Thu, Jul 22, 2021 at 7:13 AM Manivannan Sadhasivam wrote: > > Add driver support for Qualcomm PCIe Endpoint controller driver based on > the Designware core with added Qualcomm specific wrapper around the > core. The driver support is very basic such that it supports only > enumeration, PCIe read/write, and MSI. There is no ASPM and PM support > for now but these will be added later. > > The driver is capable of using the PERST# and WAKE# side-band GPIOs for > operation and written on top of the DWC PCI framework. > > Co-developed-by: Siddartha Mohanadoss > Signed-off-by: Siddartha Mohanadoss > [mani: restructured the driver and fixed several bugs for upstream] > Signed-off-by: Manivannan Sadhasivam > --- > drivers/pci/controller/dwc/Kconfig | 10 + > drivers/pci/controller/dwc/Makefile | 1 + > drivers/pci/controller/dwc/pcie-qcom-ep.c | 710 ++++++++++++++++++++++ > 3 files changed, 721 insertions(+) > create mode 100644 drivers/pci/controller/dwc/pcie-qcom-ep.c Reviewed-by: Rob Herring