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From: Rob Herring <robh+dt@kernel.org>
To: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
	PCI <linux-pci@vger.kernel.org>,
	devicetree@vger.kernel.org,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Jaehoon Chung <jh80.chung@samsung.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@ti.com>
Subject: Re: [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
Date: Mon, 26 Oct 2020 13:50:12 -0500
Message-ID: <CAL_JsqLUT7aLnQsLvcCOHCaoVAao9VSmEhoscBxu3ARXX33zrA@mail.gmail.com> (raw)
In-Reply-To: <20201023075744.26200-5-m.szyprowski@samsung.com>

On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
>
> From: Jaehoon Chung <jh80.chung@samsung.com>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
> variant found in the Exynos5433 SoCs.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
>            onto current kernel code, rewrote commit message]
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
>  drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
>  1 file changed, 112 insertions(+), 192 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
> index 7e28b1aea0d1..d91de323dd0e 100644
> --- a/drivers/phy/samsung/phy-exynos-pcie.c
> +++ b/drivers/phy/samsung/phy-exynos-pcie.c
> @@ -4,70 +4,41 @@
>   *
>   * Phy provider for PCIe controller on Exynos SoC series
>   *
> - * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
>   * Jaehoon Chung <jh80.chung@samsung.com>
>   */
>
> -#include <linux/delay.h>
>  #include <linux/io.h>
> -#include <linux/iopoll.h>
> -#include <linux/init.h>
>  #include <linux/mfd/syscon.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
>  #include <linux/phy/phy.h>
>  #include <linux/regmap.h>
>
> -/* PCIe Purple registers */
> -#define PCIE_PHY_GLOBAL_RESET          0x000
> -#define PCIE_PHY_COMMON_RESET          0x004
> -#define PCIE_PHY_CMN_REG               0x008
> -#define PCIE_PHY_MAC_RESET             0x00c
> -#define PCIE_PHY_PLL_LOCKED            0x010
> -#define PCIE_PHY_TRSVREG_RESET         0x020
> -#define PCIE_PHY_TRSV_RESET            0x024
> -
> -/* PCIe PHY registers */
> -#define PCIE_PHY_IMPEDANCE             0x004
> -#define PCIE_PHY_PLL_DIV_0             0x008
> -#define PCIE_PHY_PLL_BIAS              0x00c
> -#define PCIE_PHY_DCC_FEEDBACK          0x014
> -#define PCIE_PHY_PLL_DIV_1             0x05c
> -#define PCIE_PHY_COMMON_POWER          0x064
> -#define PCIE_PHY_COMMON_PD_CMN         BIT(3)
> -#define PCIE_PHY_TRSV0_EMP_LVL         0x084
> -#define PCIE_PHY_TRSV0_DRV_LVL         0x088
> -#define PCIE_PHY_TRSV0_RXCDR           0x0ac
> -#define PCIE_PHY_TRSV0_POWER           0x0c4
> -#define PCIE_PHY_TRSV0_PD_TSV          BIT(7)
> -#define PCIE_PHY_TRSV0_LVCC            0x0dc
> -#define PCIE_PHY_TRSV1_EMP_LVL         0x144
> -#define PCIE_PHY_TRSV1_RXCDR           0x16c
> -#define PCIE_PHY_TRSV1_POWER           0x184
> -#define PCIE_PHY_TRSV1_PD_TSV          BIT(7)
> -#define PCIE_PHY_TRSV1_LVCC            0x19c
> -#define PCIE_PHY_TRSV2_EMP_LVL         0x204
> -#define PCIE_PHY_TRSV2_RXCDR           0x22c
> -#define PCIE_PHY_TRSV2_POWER           0x244
> -#define PCIE_PHY_TRSV2_PD_TSV          BIT(7)
> -#define PCIE_PHY_TRSV2_LVCC            0x25c
> -#define PCIE_PHY_TRSV3_EMP_LVL         0x2c4
> -#define PCIE_PHY_TRSV3_RXCDR           0x2ec
> -#define PCIE_PHY_TRSV3_POWER           0x304
> -#define PCIE_PHY_TRSV3_PD_TSV          BIT(7)
> -#define PCIE_PHY_TRSV3_LVCC            0x31c
> -
> -struct exynos_pcie_phy_data {
> -       const struct phy_ops    *ops;
> -};
> +#define PCIE_PHY_OFFSET(x)             ((x) * 0x4)
> +
> +/* Sysreg FSYS register offsets and bits for Exynos5433 */
> +#define PCIE_EXYNOS5433_PHY_MAC_RESET          0x0208
> +#define PCIE_MAC_RESET_MASK                    0xFF
> +#define PCIE_MAC_RESET                         BIT(4)
> +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON       0x1010
> +#define PCIE_REFCLK_GATING_EN                  BIT(0)
> +#define PCIE_EXYNOS5433_PHY_COMMON_RESET       0x1020
> +#define PCIE_PHY_RESET                         BIT(0)
> +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET       0x1040
> +#define PCIE_GLOBAL_RESET                      BIT(0)

Resets, why is this block not a reset provider?

> +#define PCIE_REFCLK                            BIT(1)
> +#define PCIE_REFCLK_MASK                       0x16
> +#define PCIE_APP_REQ_EXIT_L1_MODE              BIT(5)

  parent reply index

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20201023075754eucas1p2ee617893ba13493236814235c619bc56@eucas1p2.samsung.com>
2020-10-23  7:57 ` [PATCH v2 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
     [not found]   ` <CGME20201023075754eucas1p2a4c9c5467f25a575bec34984fe6bb43b@eucas1p2.samsung.com>
2020-10-23  7:57     ` [PATCH v2 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding Marek Szyprowski
2020-10-24  2:59       ` Jingoo Han
     [not found]   ` <CGME20201023075755eucas1p290b7bc020e46b86fe5e7591877f87117@eucas1p2.samsung.com>
2020-10-23  7:57     ` [PATCH v2 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Marek Szyprowski
2020-10-23  9:26       ` Krzysztof Kozlowski
     [not found]   ` <CGME20201023075755eucas1p165641c7528ea987a2e1d9d28198c0e9e@eucas1p1.samsung.com>
2020-10-23  7:57     ` [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Marek Szyprowski
2020-10-23  9:28       ` Krzysztof Kozlowski
     [not found]   ` <CGME20201023075756eucas1p2c27cc3e6372127d107e5b84c810ba98f@eucas1p2.samsung.com>
2020-10-23  7:57     ` [PATCH v2 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
2020-10-24  3:00       ` Jingoo Han
2020-10-26 18:50       ` Rob Herring [this message]
2020-10-27 12:28         ` Marek Szyprowski
     [not found]   ` <CGME20201023075756eucas1p18765653e747842eef4b438aff32ef136@eucas1p1.samsung.com>
2020-10-23  7:57     ` [PATCH v2 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-23 15:09       ` kernel test robot
2020-10-24  3:12       ` Jingoo Han
2020-10-26  2:49         ` Jaehoon Chung
2020-10-26  4:08           ` Jingoo Han
2020-10-26 19:14       ` Rob Herring
2020-10-27 12:04         ` Marek Szyprowski
2020-10-27 13:24           ` Marek Szyprowski
     [not found]   ` <CGME20201023075757eucas1p13e4e7f5177bd3f789ac0d2a8aa57c86e@eucas1p1.samsung.com>
2020-10-23  7:57     ` [PATCH v2 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Marek Szyprowski

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