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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Marek Vasut <marek.vasut@gmail.com>
Cc: linux-pci <linux-pci@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Wolfram Sang <wsa@the-dreams.de>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH] PCI: rcar: Add L1 link state fix into data abort hook
Date: Mon, 14 Sep 2020 12:11:54 +0200	[thread overview]
Message-ID: <CAMuHMdWW6sX+4Hn8wdkCj0kixRZcDKiZR987iEcXrs+U+-4yUA@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdUBOOwpNLWLKX2obnezrZmOi2Uk+drvzo4KRU2H1xfJDQ@mail.gmail.com>

On Mon, Sep 14, 2020 at 11:29 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Sat, Sep 12, 2020 at 11:19 PM <marek.vasut@gmail.com> wrote:
> > From: Marek Vasut <marek.vasut+renesas@gmail.com>
> >
> > The R-Car PCIe controller is capable of handling L0s/L1 link states.
> > While the controller can enter and exit L0s link state, and exit L1
> > link state, without any additional action from the driver, to enter
> > L1 link state, the driver must complete the link state transition by
> > issuing additional commands to the controller.
> >
> > The problem is, this transition is not atomic. The controller sets
> > PMEL1RX bit in PMSR register upon reception of PM_ENTER_L1 DLLP from
> > the PCIe card, but then the controller enters some sort of inbetween
> > state. The driver must detect this condition and complete the link
> > state transition, by setting L1IATN bit in PMCTLR and waiting for
> > the link state transition to complete.
> >
> > If a PCIe access happens inside of this window, where the controller
> > is inbetween L0 and L1 link states, the access generates a fault and
> > the ARM 'imprecise external abort' handler is invoked.
> >
> > Just like other PCI controller drivers, here we hook the fault handler,
> > perform the fixup to help the controller enter L1 link state, and then
> > restart the instruction which triggered the fault. Since the controller
> > is in L1 link state now, the link can exit from L1 link state to L0 and
> > successfully complete the access.
> >
> > Note that this fixup is applicable only to Aarch32 R-Car controllers,
> > the Aarch64 R-Car perform the same fixup in TFA, see TFA commit
> > 0969397f2 ("rcar_gen3: plat: Prevent PCIe hang during L1X config access")
> >
> > Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

>
> > +        */
> > +       hook_fault_code(16 + 6, rcar_pcie_aarch32_abort_handler, SIGBUS, 0,
>
> After changing the "16 + 6" to "17", like pci-keystone.c does, it works!

Oh, this depends on LPAE.  So it must be 17 if CONFIG_ARM_LPAE=y,
22 otherwise.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

      reply	other threads:[~2020-09-14 10:12 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-12 21:18 marek.vasut
2020-09-13 17:22 ` Bjorn Helgaas
2020-09-14  1:36   ` Marek Vasut
2020-09-14  4:01     ` Bjorn Helgaas
2020-09-16 13:50       ` Marek Vasut
2020-11-19 16:25   ` Lorenzo Pieralisi
2020-11-29 13:02     ` Marek Vasut
2020-09-14  9:29 ` Geert Uytterhoeven
2020-09-14 10:11   ` Geert Uytterhoeven [this message]

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