From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC483CA9EAF for ; Thu, 24 Oct 2019 03:45:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A6F5F2166E for ; Thu, 24 Oct 2019 03:45:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lixom-net.20150623.gappssmtp.com header.i=@lixom-net.20150623.gappssmtp.com header.b="np4oLXeE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392948AbfJXDpN (ORCPT ); Wed, 23 Oct 2019 23:45:13 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:38005 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392926AbfJXDpM (ORCPT ); Wed, 23 Oct 2019 23:45:12 -0400 Received: by mail-io1-f68.google.com with SMTP id u8so27696558iom.5 for ; Wed, 23 Oct 2019 20:45:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lixom-net.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=mD92XtRViE3fuwX27/t4J88Vliq5/m5DxH+E0QdDcfY=; b=np4oLXeE8XD06z6WLNxROOXayg/7ADY4dvhHQRnY2EXH3D4wrZ4uvVBzCLMBAl1YKs X3kjp8uzPDq4VFJgPdRFGu+FIl4wDfiqtU7w6PZp+88i4oloYYBmdlOIiElf/8JWsI1Z Asi6bKnndFHWV2XnQ7GtzdTCxFqXBosXW6SW7BTP4mM/aa8KaGla/jn36tffYO0Wt5WZ v07XyDQEpncMj1ATg9d8591dV5+amUkJ8XZE3wwTs15BAh2IP3CMjZNWG3jRNsPU2znN nUG3QgiKea3A6gmmbuQUPKoqxBCEyOdOKc4JWkScnPgEO4NAoOElT2mBNY1hnetWB3TF uPIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=mD92XtRViE3fuwX27/t4J88Vliq5/m5DxH+E0QdDcfY=; b=VZ+4lh+wSmG0JNJruSDzm8reALQas66CqUbLKNdd849pA+Alkv46x8szSWdLXelE/R nArZI+clGno1HhYzsDOaCkGgOESkuVjTYYIY/5JaPiDAvQuPG2mQGfwn0vr6w0hhObcf Yn2xzuNsYCVF98abBRJ8/vEXn9EFrpqr2SzGpsbH8eqUKbeRzgSwxKcqIuok9CEHQgTH G5ctoAjkmcfbyeEWEtd+31rWzJFr/2U0aH63XZiuQxf+oPhcTWP23nXKDkqXg9Vtkvbe TrKegoYIn/eFHmnU+vwrWcw7rnVCZp1HBYJ/K2eA9TNElngqAwP+rVmywNcKkOAdcKP9 NWig== X-Gm-Message-State: APjAAAUdqrWwoztZ6TDqLSfeqsvn3XyFYtGyB1oFarwI74uY4kZDXBkq fVhe2RyG934bovlPSeXnzqtIE9IUINKXj12Yt9jr4A== X-Google-Smtp-Source: APXvYqwrUjk8l2F1yVqbPWkm0wkJV8sufdaMmeDVQTVHJSKP7u8y4ic/BWRmmzodfowZBBFsGH12nFuVxyoZKg2IkUo= X-Received: by 2002:a5d:87ce:: with SMTP id q14mr985334ios.278.1571888711746; Wed, 23 Oct 2019 20:45:11 -0700 (PDT) MIME-Version: 1.0 References: <20191023192205.97024-1-olof@lixom.net> <20191024023704.GA3152@redsun51.ssa.fujisawa.hgst.com> In-Reply-To: <20191024023704.GA3152@redsun51.ssa.fujisawa.hgst.com> From: Olof Johansson Date: Wed, 23 Oct 2019 20:45:00 -0700 Message-ID: Subject: Re: [PATCH] PCI/DPC: Add pcie_ports=dpc-native parameter to bring back old behavior To: Keith Busch Cc: Bjorn Helgaas , Keith Busch , linux-pci@vger.kernel.org, Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Wed, Oct 23, 2019 at 7:37 PM Keith Busch wrote: > > On Wed, Oct 23, 2019 at 12:22:05PM -0700, Olof Johansson wrote: > > In commit eed85ff4c0da7 ("PCI/DPC: Enable DPC only if AER is available"), > > the behavior was changed such that native (kernel) handling of DPC > > got tied to whether the kernel also handled AER. While this is what > > the standard recommends, there are BIOSes out there that lack the DPC > > handling since it was never required in the past. > > > > To make DPC still work on said platforms the same way they did before, > > add a "pcie_ports=dpc-native" kernel parameter that can be passed in > > if needed, while keeping defaults unchanged. > > If platform firmware wants to handle AER events, but the kernel enables > the DPC capability, the ports will be trapping events that firmware is > expecting to handle. Not that that's a bad thing: firmware is generally > worse at handling these errors. Right, and in particular (and what I'm looking for here): It brings back the older behavior that some platforms rely on. :-/ > > +/* > > + * If the user specified "pcie_ports=dpc-native", use the PCIe services > > + * for DPC, but cuse platform defaults for the others. > > s/cuse/use Thanks > > @@ -1534,9 +1534,11 @@ static inline int pci_irqd_intx_xlate(struct irq_domain *d, > > #ifdef CONFIG_PCIEPORTBUS > > extern bool pcie_ports_disabled; > > extern bool pcie_ports_native; > > +extern bool pcie_ports_dpc_native; > > #else > > #define pcie_ports_disabled true > > #define pcie_ports_native false > > +#define pcie_ports_dpc_native false > > #endif > > You do not have any references to pcie_ports_dpc_native outside of files that > require CONFIG_PCIEPORTBUS, so no need to define a default. If these are the only comments, maybe Bjorn can fixup when applying. Bjorn; let me know if you prefer that or if you want a fresh version. Either is fine with me. -Olof