From: Dan Williams <firstname.lastname@example.org>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: email@example.com, Linux PCI <firstname.lastname@example.org>,
Linux Kernel Mailing List <email@example.com>,
Linux ACPI <firstname.lastname@example.org>
Subject: Re: [PATCH 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root
Date: Tue, 11 May 2021 23:29:32 -0700 [thread overview]
Message-ID: <CAPcyv4hhYJsTaRbCXKQaHWw8KwfOFxa-pG4x2r8HCYqVTshZCA@mail.gmail.com> (raw)
On Mon, May 10, 2021 at 7:58 AM Jonathan Cameron
> On Fri, 7 May 2021 15:51:47 -0700
> Dan Williams <email@example.com> wrote:
> > While CXL builds upon the PCI software model for dynamic enumeration and
> > control, a static platform component is required to bootstrap the CXL
> > memory layout. In addition to identifying the host bridges ACPI is
> > responsible for enumerating the CXL memory space that can be addressed
> > by decoders. This is similar to the requirement for ACPI to publish
> > resources reported by _CRS for PCI host bridges.
> > Introduce the cxl_root object as an abstract "port" into the CXL.mem
> > address space described by HDM decoders identified by the ACPI
> > CEDT.CHBS.
> > For now just establish the initial boilerplate and sysfs attributes, to
> > be followed by enumeration of the ports within the host bridge.
> > Note the allocation of CXL core device objects is split into separate
> > alloc and add steps in order to separate the alloc error path (kfree())
> > from the device add error path (put_device()).
> > Signed-off-by: Dan Williams <firstname.lastname@example.org>
> Hi Dan
> Just one bit in here that confused me (assuming I'm reading the code correctly).
> You have is_visible for the dev_attr_supports_pmem etc to only show them if
> the particular space supports that memory type. That's fine. You also have
> the actual sysfs function checking the same flag to decide to return "1" or "0"
> which would also be fine, but in combination it's rather odd as the sysfs
> read function can never return "0" (sysfs attribute isn't visible in that
> condition). Probably deserves at least a comment.
That was deliberate since it's trivial to code and allows the
visibility policy to change without needing to go audit the attributes
that assumed invisibility. However, yes, it deserves a comment to save
brain cycles with that "hmm, that's odd" in the future.
> This also needs some documentation for the new sysfs ABI
> (Documentation/ABI/...) but that can be in a separate patch.
> Otherwise looks good to me.
next prev parent reply other threads:[~2021-05-12 6:29 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-07 22:51 [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14 Dan Williams
2021-05-07 22:51 ` [PATCH 1/8] cxl/mem: Move some definitions to mem.h Dan Williams
2021-05-10 15:14 ` Jonathan Cameron
2021-05-12 6:20 ` Dan Williams
2021-05-07 22:51 ` [PATCH 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices Dan Williams
2021-05-10 15:17 ` Jonathan Cameron
2021-05-12 6:26 ` Dan Williams
2021-05-07 22:51 ` [PATCH 3/8] cxl/core: Rename bus.c to core.c Dan Williams
2021-05-10 15:17 ` Jonathan Cameron
2021-05-07 22:51 ` [PATCH 4/8] cxl/core: Refactor CXL register lookup for bridge reuse Dan Williams
2021-05-07 22:51 ` [PATCH 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root Dan Williams
2021-05-10 14:56 ` Jonathan Cameron
2021-05-12 6:29 ` Dan Williams [this message]
2021-05-07 22:51 ` [PATCH 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS Dan Williams
2021-05-10 15:18 ` Jonathan Cameron
2021-05-07 22:51 ` [PATCH 7/8] cxl/port: Introduce cxl_port objects Dan Williams
2021-05-08 2:24 ` kernel test robot
2021-05-10 15:21 ` Jonathan Cameron
2021-05-12 6:36 ` Dan Williams
2021-05-07 22:52 ` [PATCH 8/8] cxl/acpi: Add module parameters to stand in for ACPI tables Dan Williams
2021-05-10 17:22 ` [PATCH v3 0/8] CXL Port Enumeration and Plans for v5.14 Jonathan Cameron
2021-05-10 17:31 ` Dan Williams
-- strict thread matches above, loose matches on Subject: below --
2021-03-24 21:30 [PATCH 0/8] CXL Port Enumeration Dan Williams
2021-03-24 21:30 ` [PATCH 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root Dan Williams
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