From: Dan Williams <dan.j.williams@intel.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: Dave Jiang <dave.jiang@intel.com>, Vinod Koul <vkoul@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Greg KH <gregkh@linuxfoundation.org>,
Arnd Bergmann <arnd@arndb.de>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
X86 ML <x86@kernel.org>,
dmaengine@vger.kernel.org, "Raj, Ashok" <ashok.raj@intel.com>,
Fenghua Yu <fenghua.yu@intel.com>,
linux-pci@vger.kernel.org, "Luck, Tony" <tony.luck@intel.com>,
Jing Lin <jing.lin@intel.com>,
Sanjay K Kumar <sanjay.k.kumar@intel.com>
Subject: Re: [PATCH 3/6] pci: add PCI quirk cmdmem fixup for Intel DSA device
Date: Wed, 1 Apr 2020 19:20:59 -0700 [thread overview]
Message-ID: <CAPcyv4iE_-g8ymYe75bLKmVUvTVtp8GJm3xqUoiscbyTxoUnbQ@mail.gmail.com> (raw)
In-Reply-To: <20200401071851.GA31076@infradead.org>
On Wed, Apr 1, 2020 at 12:19 AM Christoph Hellwig <hch@infradead.org> wrote:
>
> On Mon, Mar 30, 2020 at 02:27:06PM -0700, Dave Jiang wrote:
> > Since there is no standard way that defines a PCI device that receives
> > descriptors or commands with synchronous write operations, add quirk to set
> > cmdmem for the Intel accelerator device that supports it.
>
> Why do we need a quirk for this? Even assuming a flag is needed in
> struct pci_dev (and I don't really understand why that is needed to
> start with), it could be set in ->probe.
The consideration in my mind is whether this new memory type and
instruction combination warrants a new __attribute__((noderef,
address_space(X))) separate from __iomem. If it stays a single device
concept layered on __iomem then yes, I agree it can all live locally
in the driver. However, when / if this facility becomes wider spread,
as the PCI ECR in question is trending, it might warrant general
annotation.
The enqcmds instruction does not operate on typical x86 mmio
addresses, only these special device portals offer the ability to have
non-posted writes with immediate results in the cpu condition code
flags.
next prev parent reply other threads:[~2020-04-02 2:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 21:26 [PATCH 0/6] Add shared workqueue support for idxd driver Dave Jiang
2020-03-30 21:26 ` [PATCH 1/6] x86/asm: add iosubmit_cmds512_sync() based on enqcmds Dave Jiang
2020-03-30 21:27 ` [PATCH 2/6] device/pci: add cmdmem cap to pci_dev Dave Jiang
2020-03-31 10:04 ` Greg KH
2020-03-31 17:07 ` Dave Jiang
2020-03-31 17:24 ` Greg KH
2020-03-31 17:38 ` Dave Jiang
2020-03-31 16:03 ` Bjorn Helgaas
2020-03-31 21:44 ` Dave Jiang
2020-03-30 21:27 ` [PATCH 3/6] pci: add PCI quirk cmdmem fixup for Intel DSA device Dave Jiang
2020-03-31 15:59 ` Bjorn Helgaas
2020-03-31 18:02 ` Dave Jiang
2020-04-01 7:18 ` Christoph Hellwig
2020-04-02 2:20 ` Dan Williams [this message]
2020-04-02 7:39 ` Christoph Hellwig
2020-03-30 21:27 ` [PATCH 4/6] device: add cmdmem support for MMIO address Dave Jiang
2020-04-01 7:19 ` Christoph Hellwig
2020-03-30 21:27 ` [PATCH 5/6] dmaengine: idxd: add shared workqueue support Dave Jiang
2020-03-30 21:27 ` [PATCH 6/6] dmaengine: idxd: add ABI documentation for shared wq Dave Jiang
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