From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Andrew Murray <andrew.murray@arm.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
Leo Li <leoyang.li@nxp.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"M.h. Lian" <minghuan.lian@nxp.com>
Subject: RE: [PATCHv2 1/4] dt-bindings: PCI: designware: Remove the num-lanes from Required properties
Date: Tue, 20 Aug 2019 10:04:29 +0000 [thread overview]
Message-ID: <DB8PR04MB6747E55FD982EE4C856DF30D84AB0@DB8PR04MB6747.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20190820092251.GE23903@e119886-lin.cambridge.arm.com>
Hi Andrew,
Thanks a lot for your review!
Thanks,
Zhiqiang
> -----Original Message-----
> From: Andrew Murray <andrew.murray@arm.com>
> Sent: 2019年8月20日 17:23
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; gustavo.pimentel@synopsys.com;
> jingoohan1@gmail.com; bhelgaas@google.com; robh+dt@kernel.org;
> mark.rutland@arm.com; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; lorenzo.pieralisi@arm.com; M.h. Lian
> <minghuan.lian@nxp.com>
> Subject: Re: [PATCHv2 1/4] dt-bindings: PCI: designware: Remove the
> num-lanes from Required properties
>
> On Tue, Aug 20, 2019 at 07:28:43AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > The num-lanes is not a mandatory property, e.g. on FSL Layerscape
> > SoCs, the PCIe link training is completed automatically base on the
> > selected SerDes protocol, it doesn't need the num-lanes to set-up the
> > link width.
> >
> > It is previously in both Required and Optional properties, let's
> > remove it from the Required properties.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > ---
>
> Reviewed-by: Andrew Murray <andrew.murray@arm.com>
>
>
> > V2:
> > - Reworded the change log and subject.
> > - Fixed a typo in subject.
> >
> > Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 -
> > 1 file changed, 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > index 5561a1c060d0..bd880df39a79 100644
> > --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
> > @@ -11,7 +11,6 @@ Required properties:
> > the ATU address space.
> > (The old way of getting the configuration address space from
> "ranges"
> > is deprecated and should be avoided.)
> > -- num-lanes: number of lanes to use
> > RC mode:
> > - #address-cells: set to <3>
> > - #size-cells: set to <2>
> > --
> > 2.17.1
> >
next prev parent reply other threads:[~2019-08-20 10:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-20 7:28 [PATCHv2 0/4] Layerscape: Remove num-lanes property from PCIe nodes Z.q. Hou
2019-08-20 7:28 ` [PATCHv2 1/4] dt-bindings: PCI: designware: Remove the num-lanes from Required properties Z.q. Hou
2019-08-20 9:22 ` Andrew Murray
2019-08-20 10:04 ` Z.q. Hou [this message]
2019-08-22 17:31 ` Lorenzo Pieralisi
2019-08-27 16:57 ` Rob Herring
2019-08-28 3:43 ` Z.q. Hou
2019-08-20 7:28 ` [PATCHv2 2/4] PCI: dwc: Return directly when num-lanes is not found Z.q. Hou
2019-08-20 7:28 ` [PATCHv2 3/4] ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes Z.q. Hou
2019-08-20 7:29 ` [PATCHv2 4/4] arm64: dts: fsl: " Z.q. Hou
2019-08-22 16:48 ` [PATCHv2 0/4] Layerscape: " Lorenzo Pieralisi
2019-08-23 9:44 ` Andrew Murray
2019-08-23 10:35 ` Lorenzo Pieralisi
2019-08-23 11:07 ` Lorenzo Pieralisi
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