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Tue, 3 Nov 2020 02:49:27 +0000 Received: from MWHPR11MB1645.namprd11.prod.outlook.com ([fe80::f8e3:1ce2:fcb2:29b5]) by MWHPR11MB1645.namprd11.prod.outlook.com ([fe80::f8e3:1ce2:fcb2:29b5%8]) with mapi id 15.20.3499.030; Tue, 3 Nov 2020 02:49:27 +0000 From: "Tian, Kevin" To: Jason Gunthorpe , "Jiang, Dave" CC: Bjorn Helgaas , "vkoul@kernel.org" , "Dey, Megha" , "maz@kernel.org" , "bhelgaas@google.com" , "tglx@linutronix.de" , "alex.williamson@redhat.com" , "Pan, Jacob jun" , "Raj, Ashok" , "Liu, Yi L" , "Lu, Baolu" , "Kumar, Sanjay K" , "Luck, Tony" , "jing.lin@intel.com" , "Williams, Dan J" , "kwankhede@nvidia.com" , "eric.auger@redhat.com" , "parav@mellanox.com" , "rafael@kernel.org" , "netanelg@mellanox.com" , "shahafs@mellanox.com" , "yan.y.zhao@linux.intel.com" , "pbonzini@redhat.com" , "Ortiz, Samuel" , "Hossain, Mona" , "dmaengine@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , "kvm@vger.kernel.org" Subject: RE: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection Thread-Topic: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection Thread-Index: AQHWru26nCdjGLbk80+ZhPfx8iZ806mwjmaAgAAYm4CAABfkAIAAARAAgAQYdwCAAOAGcA== Date: Tue, 3 Nov 2020 02:49:27 +0000 Message-ID: References: <20201030195159.GA589138@bjorn-Precision-5520> <71da5f66-e929-bab1-a1c6-a9ac9627a141@intel.com> <20201030224534.GN2620339@nvidia.com> <20201102132158.GA3352700@nvidia.com> In-Reply-To: <20201102132158.GA3352700@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: nvidia.com; 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x-ms-exchange-antispam-messagedata: 0lCvFjfnSkq4+ButBtKrN8d28ab44inaVZMg7fF8aLklpDZEuvD+GgtJXT/NASobPMoe37CqZtZjJKc3NEWbNz2iyR/XFkp2YvRRioaRBkXb2dScXmgMj5mOUhBsICLposjTJo7F4+HjQDQvqQ6JhUNv4b6G8sfrXFFzfPv+rNjzPH4ByUhnKEiZDZLdYSAoMv5b5TMYIYpJQNJUvv2f2j7upqNTTHuOW3LzwOhZg7UlpyX+kixyD6V6P7D+CtLXJQtlAvHkI9KumpY2GsLKhTY6Wg3CiYc6hic2vf0/DMJbL2lPZhtCKK3B/K3RBUp6tNnsQNO9+JnYqrHTfUYO7xgHTikjFpPYVNGSr+vwd+1hymfztoRzIPjvgy/E4+FwN8ESy5qu51DdS7hCtP9p2cNnlclzhYUB8h++1rJmgwGpeSyFDY77LZdozR/NOmUtxD7WG0wzLxe9jahZzvuv2tVrWzG0yGaT0u0G9pS8JWmWEIc90YWNbGzX+VG4O63tCI/SeNyUSk2qD5G4wh31e4ZqplEl1t3A1CksoDw4KE5swQxVx0nydqyT4Eiel9F8rx9NF2Bn7s9+pWmmSV0nvEo0FsJ+8CVY1ITJU6cm1zh7ZFUZVF9n9nDVn2DUPtzZ9+EZCsJ2vqOtknazb6KKIA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1645.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e4fe5fa9-f191-472f-cf99-08d87fa314d2 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Nov 2020 02:49:27.6393 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5f8qzreQDmCVmRXAp5ExrsiL/Py6OuP1Tizp2bLKDpbNvsD69is6MKHbi4VeuEWqsIcNSuxA9eSk1Gycxp+VXg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB0014 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org > From: Jason Gunthorpe > Sent: Monday, November 2, 2020 9:22 PM >=20 > On Fri, Oct 30, 2020 at 03:49:22PM -0700, Dave Jiang wrote: > > > > > > On 10/30/2020 3:45 PM, Jason Gunthorpe wrote: > > > On Fri, Oct 30, 2020 at 02:20:03PM -0700, Dave Jiang wrote: > > > > So the intel-iommu driver checks for the SIOV cap. And the idxd dri= ver > > > > checks for SIOV and IMS cap. There will be other upcoming drivers t= hat > will > > > > check for such cap too. It is Intel vendor specific right now, but = SIOV is > > > > public and other vendors may implement to the spec. Is there a good > place to > > > > put the common capability check for that? > > > > > > I'm still really unhappy with these SIOV caps. It was explained this > > > is just a hack to make up for pci_ims_array_create_msi_irq_domain() > > > succeeding in VM cases when it doesn't actually work. > > > > > > Someday this is likely to get fixed, so tying platform behavior to PC= I > > > caps is completely wrong. > > > > > > This needs to be solved in the platform code, > > > pci_ims_array_create_msi_irq_domain() should not succeed in these > > > cases. > > > > That sounds reasonable. Are you asking that the IMS cap check should ga= te > > the success/failure of pci_ims_array_create_msi_irq_domain() rather tha= n > the > > driver? >=20 > There shouldn't be an IMS cap at all >=20 > As I understand, the problem here is the only way to establish new > VT-d IRQ routing is by trapping and emulating MSI/MSI-X related > activities and triggering routing of the vectors into the guest. >=20 > There is a missing hypercall to allow the guest to do this on its own, > presumably it will someday be fixed so IMS can work in guests. Hypercall is VMM specific, while IMS cap provides a VMM-agnostic interface so any guest driver (if following the spec) can seamlessly work on all hypervisors. Thanks Kevin