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Wed, 31 Mar 2021 05:28:47 +0000 From: "Thokala, Srikanth" To: Lorenzo Pieralisi CC: "bhelgaas@google.com" , "robh+dt@kernel.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "andriy.shevchenko@linux.intel.com" , "mgross@linux.intel.com" , "Raja Subramanian, Lakshmi Bai" , "Sangannavar, Mallikarjunappa" , "kw@linux.com" , "maz@kernel.org" , "gustavo.pimentel@synopsys.com" Subject: RE: [PATCH v8 2/2] PCI: keembay: Add support for Intel Keem Bay Thread-Topic: [PATCH v8 2/2] PCI: keembay: Add support for Intel Keem Bay Thread-Index: AQHXBVou+XdwLl2NikywEE1XCJLSHqqbLjiAgAKWgZA= Date: Wed, 31 Mar 2021 05:28:47 +0000 Message-ID: References: <20210218021757.21931-1-srikanth.thokala@intel.com> <20210218021757.21931-3-srikanth.thokala@intel.com> <20210329130725.GA4983@e121166-lin.cambridge.arm.com> In-Reply-To: <20210329130725.GA4983@e121166-lin.cambridge.arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: arm.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5595.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2de28f9b-060c-4a32-351e-08d8f405dbe3 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Mar 2021 05:28:47.0684 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: a7Z8GnCFbEsQPyXdoy9T/lUf6wgY0aoZOUOUdnp5L877vzMzGdjFeNuRechi65kZM0Re2MP7juitRwYkJDLXAY4PYIVAjdMpntb8315evsE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5611 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi Lorenzo, Thank you for your time in reviewing the patch. > -----Original Message----- > From: Lorenzo Pieralisi > Sent: Monday, March 29, 2021 6:37 PM > To: Thokala, Srikanth > Cc: bhelgaas@google.com; robh+dt@kernel.org; linux-pci@vger.kernel.org; > devicetree@vger.kernel.org; andriy.shevchenko@linux.intel.com; > mgross@linux.intel.com; Raja Subramanian, Lakshmi Bai > ; Sangannavar, Mallikarjunappa > ; kw@linux.com; maz@kernel.org; > gustavo.pimentel@synopsys.com > Subject: Re: [PATCH v8 2/2] PCI: keembay: Add support for Intel Keem Bay >=20 > [+ Marc, Gustavo] >=20 > On Thu, Feb 18, 2021 at 07:47:57AM +0530, srikanth.thokala@intel.com > wrote: > > +static irqreturn_t keembay_pcie_irq_handler(int irq, void *arg) > > +{ > > + struct keembay_pcie *pcie =3D arg; > > + struct dw_pcie *pci =3D &pcie->pci; > > + struct pcie_port *pp =3D &pci->pp; > > + u32 val, mask, status; > > + > > + val =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS); > > + mask =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > + > > + status =3D val & mask; > > + if (!status) > > + return IRQ_NONE; > > + > > + if (status & MSI_CTRL_INT) > > + dw_handle_msi_irq(pp); > > + > > + writel(status, pcie->apb_base + PCIE_REGS_INTERRUPT_STATUS); > > + > > + return IRQ_HANDLED; > > +} > > + > > +static int keembay_pcie_setup_irq(struct keembay_pcie *pcie) > > +{ > > + struct dw_pcie *pci =3D &pcie->pci; > > + struct device *dev =3D pci->dev; > > + struct platform_device *pdev =3D to_platform_device(dev); > > + int irq, ret; > > + > > + irq =3D platform_get_irq_byname(pdev, "pcie"); > > + if (irq < 0) > > + return irq; > > + > > + ret =3D devm_request_irq(dev, irq, keembay_pcie_irq_handler, > > + IRQF_SHARED | IRQF_NO_THREAD, "pcie", pcie); > Mmm. What's this "pcie" line is actually signaling ? It looks like > MSIs are reported through it and for that AFAIK the dwc core should > set-up a chained IRQ in the core code unless the pcie_port->msi_irq is > set (which is what this driver does). Yes, your understanding is correct. This ISR will handle MSI interrupts. >=20 > If DWC core code can't handle this host controller MSI logic, the > MSI handling should be setup as a chained IRQ, not an IRQ action, > this is an IRQ layering issue/abuse that came up in the past, > I don't want to add more core that relies on it. Ok, I see your point. I will make necessary changes for the next version of the patch. Thanks! Srikanth >=20 > Lorenzo >=20 > > + if (ret) > > + dev_err(dev, "Failed to request IRQ: %d\n", ret); > > + > > + return ret; > > +} > > + > > +static void keembay_pcie_ep_init(struct dw_pcie_ep *ep) > > +{ > > + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); > > + struct keembay_pcie *pcie =3D dev_get_drvdata(pci->dev); > > + > > + writel(EDMA_INT_EN, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > +} > > + > > +static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no= , > > + enum pci_epc_irq_type type, > > + u16 interrupt_num) > > +{ > > + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); > > + > > + switch (type) { > > + case PCI_EPC_IRQ_LEGACY: > > + /* Legacy interrupts are not supported in Keem Bay */ > > + dev_err(pci->dev, "Legacy IRQ is not supported\n"); > > + return -EINVAL; > > + case PCI_EPC_IRQ_MSI: > > + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); > > + case PCI_EPC_IRQ_MSIX: > > + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); > > + default: > > + dev_err(pci->dev, "Unknown IRQ type %d\n", type); > > + return -EINVAL; > > + } > > +} > > + > > +static const struct pci_epc_features keembay_pcie_epc_features =3D { > > + .linkup_notifier =3D false, > > + .msi_capable =3D true, > > + .msix_capable =3D true, > > + .reserved_bar =3D BIT(BAR_1) | BIT(BAR_3) | BIT(BAR_5), > > + .bar_fixed_64bit =3D BIT(BAR_0) | BIT(BAR_2) | BIT(BAR_4), > > + .align =3D SZ_16K, > > +}; > > + > > +static const struct pci_epc_features * > > +keembay_pcie_get_features(struct dw_pcie_ep *ep) > > +{ > > + return &keembay_pcie_epc_features; > > +} > > + > > +static const struct dw_pcie_ep_ops keembay_pcie_ep_ops =3D { > > + .ep_init =3D keembay_pcie_ep_init, > > + .raise_irq =3D keembay_pcie_ep_raise_irq, > > + .get_features =3D keembay_pcie_get_features, > > +}; > > + > > +static const struct dw_pcie_host_ops keembay_pcie_host_ops =3D { > > +}; > > + > > +static int keembay_pcie_add_pcie_port(struct keembay_pcie *pcie, > > + struct platform_device *pdev) > > +{ > > + struct dw_pcie *pci =3D &pcie->pci; > > + struct pcie_port *pp =3D &pci->pp; > > + struct device *dev =3D &pdev->dev; > > + u32 val; > > + int ret; > > + > > + pp->ops =3D &keembay_pcie_host_ops; > > + pp->msi_irq =3D -ENODEV; > > + > > + pcie->reset =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); > > + if (IS_ERR(pcie->reset)) > > + return PTR_ERR(pcie->reset); > > + > > + ret =3D keembay_pcie_probe_clocks(pcie); > > + if (ret) > > + return ret; > > + > > + val =3D readl(pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); > > + val |=3D PHY0_SRAM_BYPASS; > > + writel(val, pcie->apb_base + PCIE_REGS_PCIE_PHY_CNTL); > > + > > + writel(PCIE_DEVICE_TYPE, pcie->apb_base + PCIE_REGS_PCIE_CFG); > > + > > + ret =3D keembay_pcie_pll_init(pcie); > > + if (ret) > > + return ret; > > + > > + val =3D readl(pcie->apb_base + PCIE_REGS_PCIE_CFG); > > + writel(val | PCIE_RSTN, pcie->apb_base + PCIE_REGS_PCIE_CFG); > > + keembay_ep_reset_deassert(pcie); > > + > > + ret =3D dw_pcie_host_init(pp); > > + if (ret) { > > + keembay_ep_reset_assert(pcie); > > + dev_err(dev, "Failed to initialize host: %d\n", ret); > > + return ret; > > + } > > + > > + val =3D readl(pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > + if (IS_ENABLED(CONFIG_PCI_MSI)) > > + val |=3D MSI_CTRL_INT_EN; > > + writel(val, pcie->apb_base + PCIE_REGS_INTERRUPT_ENABLE); > > + > > + return 0; > > +} > > + > > +static int keembay_pcie_probe(struct platform_device *pdev) > > +{ > > + const struct keembay_pcie_of_data *data; > > + struct device *dev =3D &pdev->dev; > > + struct keembay_pcie *pcie; > > + struct dw_pcie *pci; > > + enum dw_pcie_device_mode mode; > > + int ret; > > + > > + data =3D device_get_match_data(dev); > > + if (!data) > > + return -ENODEV; > > + > > + mode =3D (enum dw_pcie_device_mode)data->mode; > > + > > + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > > + if (!pcie) > > + return -ENOMEM; > > + > > + pci =3D &pcie->pci; > > + pci->dev =3D dev; > > + pci->ops =3D &keembay_pcie_ops; > > + > > + pcie->mode =3D mode; > > + > > + pcie->apb_base =3D devm_platform_ioremap_resource_byname(pdev, "apb")= ; > > + if (IS_ERR(pcie->apb_base)) > > + return PTR_ERR(pcie->apb_base); > > + > > + ret =3D keembay_pcie_setup_irq(pcie); > > + if (ret) > > + return ret; > > + > > + platform_set_drvdata(pdev, pcie); > > + > > + switch (pcie->mode) { > > + case DW_PCIE_RC_TYPE: > > + if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_HOST)) > > + return -ENODEV; > > + > > + return keembay_pcie_add_pcie_port(pcie, pdev); > > + case DW_PCIE_EP_TYPE: > > + if (!IS_ENABLED(CONFIG_PCIE_KEEMBAY_EP)) > > + return -ENODEV; > > + > > + pci->ep.ops =3D &keembay_pcie_ep_ops; > > + return dw_pcie_ep_init(&pci->ep); > > + default: > > + dev_err(dev, "Invalid device type %d\n", pcie->mode); > > + return -ENODEV; > > + } > > +} > > + > > +static const struct keembay_pcie_of_data keembay_pcie_rc_of_data =3D { > > + .mode =3D DW_PCIE_RC_TYPE, > > +}; > > + > > +static const struct keembay_pcie_of_data keembay_pcie_ep_of_data =3D { > > + .mode =3D DW_PCIE_EP_TYPE, > > +}; > > + > > +static const struct of_device_id keembay_pcie_of_match[] =3D { > > + { > > + .compatible =3D "intel,keembay-pcie", > > + .data =3D &keembay_pcie_rc_of_data, > > + }, > > + { > > + .compatible =3D "intel,keembay-pcie-ep", > > + .data =3D &keembay_pcie_ep_of_data, > > + }, > > + {} > > +}; > > + > > +static struct platform_driver keembay_pcie_driver =3D { > > + .driver =3D { > > + .name =3D "keembay-pcie", > > + .of_match_table =3D keembay_pcie_of_match, > > + .suppress_bind_attrs =3D true, > > + }, > > + .probe =3D keembay_pcie_probe, > > +}; > > +builtin_platform_driver(keembay_pcie_driver); > > -- > > 2.17.1 > >