From: Jingoo Han <jingoohan1@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>,
"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"andrew.murray@arm.com" <andrew.murray@arm.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"kishon@ti.com" <kishon@ti.com>,
"thierry.reding@gmail.com" <thierry.reding@gmail.com>
Cc: "Jisheng.Zhang@synaptics.com" <Jisheng.Zhang@synaptics.com>,
"jonathanh@nvidia.com" <jonathanh@nvidia.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"kthota@nvidia.com" <kthota@nvidia.com>,
"mmaddireddy@nvidia.com" <mmaddireddy@nvidia.com>,
"sagar.tv@gmail.com" <sagar.tv@gmail.com>,
Han Jingoo <jingoohan1@gmail.com>
Subject: Re: [PATCH 0/4] Add support to defer core initialization
Date: Mon, 18 Nov 2019 16:43:58 +0000 [thread overview]
Message-ID: <SL2P216MB0105D49E39194C827D60B032AA4D0@SL2P216MB0105.KORP216.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <108c9f42-a595-515e-5ed6-e745a55efe70@nvidia.com>
On 11/18/19, 1:55 AM, Vidya Sagar wrote:
>
> On 11/13/2019 2:38 PM, Vidya Sagar wrote:
> > EPC/DesignWare core endpoint subsystems assume that the core registers are
> > available always for SW to initialize. But, that may not be the case always.
> > For example, Tegra194 hardware has the core running on a clock that is derived
> > from reference clock that is coming into the endpoint system from host.
> > Hence core is made available asynchronously based on when host system is going
> > for enumeration of devices. To accommodate this kind of hardwares, support is
> > required to defer the core initialization until the respective platform driver
> > informs the EPC/DWC endpoint sub-systems that the core is indeed available for
> > initiaization. This patch series is attempting to add precisely that.
> > This series is based on Kishon's patch that adds notification mechanism
> > support from EPC to EPF @ http://patchwork.ozlabs.org/patch/1109884/
> >
> > Vidya Sagar (4):
> > PCI: dwc: Add new feature to skip core initialization
> > PCI: endpoint: Add notification for core init completion
> > PCI: dwc: Add API to notify core initialization completion
> > PCI: pci-epf-test: Add support to defer core initialization
> >
> > .../pci/controller/dwc/pcie-designware-ep.c | 79 +++++++-----
> > drivers/pci/controller/dwc/pcie-designware.h | 11 ++
> > drivers/pci/endpoint/functions/pci-epf-test.c | 114 ++++++++++++------
> > drivers/pci/endpoint/pci-epc-core.c | 19 ++-
> > include/linux/pci-epc.h | 2 +
> > include/linux/pci-epf.h | 5 +
> > 6 files changed, 164 insertions(+), 66 deletions(-)
> >
>
> Hi Kishon / Gustavo / Jingoo,
> Could you please take a look at this patch series?
You need a Ack from Kishon, because he made EP code.
> - Vidya Sagar
next prev parent reply other threads:[~2019-11-18 16:44 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-13 9:08 [PATCH 0/4] Add support to defer core initialization Vidya Sagar
2019-11-13 9:08 ` [PATCH 1/4] PCI: dwc: Add new feature to skip " Vidya Sagar
2019-11-27 8:14 ` Kishon Vijay Abraham I
2019-11-27 8:40 ` Vidya Sagar
2019-11-27 9:18 ` Kishon Vijay Abraham I
2019-11-27 9:48 ` Christoph Hellwig
2019-11-29 14:40 ` Vidya Sagar
2019-12-05 9:59 ` Vidya Sagar
2019-12-05 10:04 ` Kishon Vijay Abraham I
2020-01-03 9:40 ` Vidya Sagar
2019-11-13 9:08 ` [PATCH 2/4] PCI: endpoint: Add notification for core init completion Vidya Sagar
2019-11-27 8:18 ` Kishon Vijay Abraham I
2019-11-27 8:22 ` Kishon Vijay Abraham I
2019-11-13 9:08 ` [PATCH 3/4] PCI: dwc: Add API to notify core initialization completion Vidya Sagar
2019-11-13 9:08 ` [PATCH 4/4] PCI: pci-epf-test: Add support to defer core initialization Vidya Sagar
2019-11-27 9:20 ` Kishon Vijay Abraham I
2019-12-01 14:29 ` Vidya Sagar
2019-12-05 11:22 ` Kishon Vijay Abraham I
2020-01-03 9:40 ` Vidya Sagar
2019-11-18 6:55 ` [PATCH 0/4] " Vidya Sagar
2019-11-18 16:43 ` Jingoo Han [this message]
2019-11-25 4:33 ` Vidya Sagar
2019-11-25 4:45 ` Kishon Vijay Abraham I
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