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From: Jingoo Han <jingoohan1@gmail.com>
To: Rob Herring <robh@kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Cc: Vidya Sagar <vidyas@nvidia.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Han Jingoo <jingoohan1@gmail.com>
Subject: Re: [PATCH] PCI: dwc: Restore ATU memory resource setup to use last entry
Date: Mon, 26 Oct 2020 16:22:25 +0000	[thread overview]
Message-ID: <SLXP216MB0477EED7E80B8738CCD233E7AA190@SLXP216MB0477.KORP216.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <20201026154852.221483-1-robh@kernel.org>

On 10/26/20, 11:48 AM, Rob Herring wrote:
> 
> Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI
> resources"), the DWC driver was setting up the last memory resource
> rather than the first memory resource. This doesn't matter for most
> platforms which only have 1 memory resource, but it broke Tegra194 which
> has a 2nd (prefetchable) memory region which requires an ATU entry. The
> first region on Tegra194 relies on the default 1:1 pass-thru of outbound
> transactions which doesn't need an ATU entry.
>
> Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
> Reported-by: Vidya Sagar <vidyas@nvidia.com>
> Cc: Jingoo Han <jingoohan1@gmail.com>

Acked-by: Jingoo Han <jingoohan1@gmail.com>

Best regards,
Jingoo Han

> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 674f32db85ca..44c2a6572199 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -586,8 +586,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  	 * ATU, so we should not program the ATU here.
>  	 */
>  	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> -		struct resource_entry *entry =
> -			resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> +		struct resource_entry *tmp, *entry = NULL;
> +
> +		/* Get last memory resource entry */
> +		resource_list_for_each_entry(tmp, &pp->bridge->windows)
> +			if (resource_type(tmp->res) == IORESOURCE_MEM)
> +				entry = tmp;
>
>  		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
>  					  PCIE_ATU_TYPE_MEM, entry->res->start,
> -- 
> 2.25.1


  reply	other threads:[~2020-10-26 16:22 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-26 15:48 Rob Herring
2020-10-26 16:22 ` Jingoo Han [this message]
2020-10-26 16:49 ` Vidya Sagar
2020-10-26 18:02   ` Rob Herring
2020-11-03 16:24 ` Lorenzo Pieralisi
2020-11-03 19:30 ` Bjorn Helgaas

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