From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>,
"horms@verge.net.au" <horms@verge.net.au>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>
Cc: "linux-renesas-soc@vger.kernel.org"
<linux-renesas-soc@vger.kernel.org>,
"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: RE: [PATCH] PCI: rcar: Fix writing the MACCTLR register value
Date: Wed, 9 Oct 2019 02:44:05 +0000 [thread overview]
Message-ID: <TYAPR01MB4544A787E2FC5BDE45FF7816D8950@TYAPR01MB4544.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <2ae9793a-2500-496f-2e18-927237fbd02a@cogentembedded.com>
Hello Sergei-san,
> From: Sergei Shtylyov, Sent: Wednesday, October 9, 2019 1:13 AM
>
> Hello!
>
> On 10/08/2019 01:18 PM, Yoshihiro Shimoda wrote:
>
> > According to the R-Car Gen2/3 manual, the bit 0 of MACCTLR register
> > should be written by 0. To avoid unexpected behaviors from this
>
> s/by/to/. I'd also mention that this bit is set to 1 on reset.
Thank you for your review! I'll fix it.
Best regards,
Yoshihiro Shimoda
> > incorrect setting, this patch fixes it.
> >
> > Fixes: b3327f7fae66 ("PCI: rcar: Try increasing PCIe link speed to 5 GT/s at boot")
> > Cc: <stable@vger.kernel.org> # v4.9+
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> [...]
>
> MBR, Sergei
prev parent reply other threads:[~2019-10-09 2:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-08 10:18 [PATCH] PCI: rcar: Fix writing the MACCTLR register value Yoshihiro Shimoda
2019-10-08 16:13 ` Sergei Shtylyov
2019-10-09 2:44 ` Yoshihiro Shimoda [this message]
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