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From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Bjorn Helgaas <helgaas@kernel.org>,
	Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Cc: "mark.rutland@arm.com" <mark.rutland@arm.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"will.deacon@arm.com" <will.deacon@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Leo Li <leoyang.li@nxp.com>, "M.h. Lian" <minghuan.lian@nxp.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	Mingkai Hu <mingkai.hu@nxp.com>,
	"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
	"shawnguo@kernel.org" <shawnguo@kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: RE: [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device
Date: Mon, 18 Feb 2019 07:15:22 +0000	[thread overview]
Message-ID: <VI1PR04MB57927A11B589323E30E45BF884630@VI1PR04MB5792.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20190208141315.GU7268@google.com>

Hi Bjorn,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: 2019年2月8日 22:13
> To: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; mark.rutland@arm.com;
> devicetree@vger.kernel.org; lorenzo.pieralisi@arm.com; Xiaowei Bao
> <xiaowei.bao@nxp.com>; linux-pci@vger.kernel.org; will.deacon@arm.com;
> linux-kernel@vger.kernel.org; Leo Li <leoyang.li@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; robh+dt@kernel.org; Mingkai Hu
> <mingkai.hu@nxp.com>; catalin.marinas@arm.com; shawnguo@kernel.org;
> linux-arm-kernel@lists.infradead.org; Thomas Petazzoni
> <thomas.petazzoni@bootlin.com>
> Subject: Re: [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device
> 
> [+cc Thomas]
> 
> On Fri, Feb 08, 2019 at 06:11:15PM +0530, Subrahmanya Lingappa wrote:
> > On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> > >
> > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > >
> > > Avoid to issue CFG transactions to link partner when the PCIe link
> > > is not up. And allow CFG transactions to all functions of Endpoint
> > > implemented multiple functions.
> > >
> > > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge
> > > IP driver")
> > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > > ---
> > > V3:
> > >  - No change
> > >
> > >  drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++-
> > >  1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > index dc5324d94466..1ae82e790562 100644
> > > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> > > @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct
> > > pci_bus *bus, unsigned int devfn)  {
> > >         struct mobiveil_pcie *pcie = bus->sysdata;
> > >
> > > +       /* If there is no link, then there is no device */
> > > +       if (bus->number > pcie->rp.root_bus_nr
> && !mobiveil_pcie_link_up(pcie))
> > > +               return false;
> > > +
> > >         /* Only one device down on each root port */
> > >         if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
> > >                 return false;
> > > @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct
> pci_bus *bus, unsigned int devfn)
> > >          * Do not read more than one device on the bus directly
> > >          * attached to RC
> > >          */
> > > -       if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
> > > +       if ((bus->primary == pcie->rp.root_bus_nr) &&
> > > + (PCI_SLOT(devfn) > 0))
> 
> > here change "primary" to "number", as it's a bug in the original driver too.
> 
> This looks like it should be split into two patches: (1) checking for link up, and
> (2) checking root_bus_nr.

Yes, will split this patch in next version.

> 
> And if you mean "bus->primary == pcie->rp.root_bus_nr" is a bug in
> pci-aardvark.c, too, it is imperative to fix that bug also (with a separate patch).

It is not a bug, but the bug is to limit multiple function EP (devfn > 0).

Thanks,
Zhiqiang

  reply	other threads:[~2019-02-18  7:15 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-29  8:08 [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-01-29  8:08 ` [PATCHv3 01/27] PCI: mobiveil: uniform the register accessors Z.q. Hou
2019-02-05  5:39   ` Subrahmanya Lingappa
2019-02-05 17:43     ` Lorenzo Pieralisi
2019-02-06 10:59       ` Subrahmanya Lingappa
2019-01-29  8:08 ` [PATCHv3 02/27] PCI: mobiveil: format the code without function change Z.q. Hou
2019-02-05  5:48   ` Subrahmanya Lingappa
2019-02-18  7:03     ` Z.q. Hou
2019-01-29  8:08 ` [PATCHv3 03/27] PCI: mobiveil: correct the returned error number Z.q. Hou
2019-02-05  5:53   ` Subrahmanya Lingappa
2019-01-29  8:08 ` [PATCHv3 04/27] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-02-05  6:05   ` Subrahmanya Lingappa
2019-02-18  7:03     ` Z.q. Hou
2019-01-29  8:09 ` [PATCHv3 05/27] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-02-05  6:06   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 06/27] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2019-02-05  6:07   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 07/27] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-02-05  6:08   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-02-05  6:08   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 09/27] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2019-02-05  6:10   ` Subrahmanya Lingappa
2019-02-18  7:07     ` Z.q. Hou
2019-01-29  8:09 ` [PATCHv3 10/27] PCI: mobiveil: fix the INTx process error Z.q. Hou
2019-02-05  6:11   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 11/27] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2019-02-05  6:11   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 12/27] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2019-02-05  6:12   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 13/27] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2019-02-08 12:30   ` Subrahmanya Lingappa
2019-01-29  8:09 ` [PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2019-02-08 12:31   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 15/27] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2019-02-08 12:32   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 16/27] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-02-08 12:37   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2019-02-08 12:41   ` Subrahmanya Lingappa
2019-02-08 14:13     ` Bjorn Helgaas
2019-02-18  7:15       ` Z.q. Hou [this message]
2019-02-18  7:04     ` Z.q. Hou
2019-01-29  8:10 ` [PATCHv3 18/27] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2019-02-08 12:41   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 19/27] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2019-02-08 12:42   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2019-02-08 12:44   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 21/27] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2019-02-08 12:46   ` Subrahmanya Lingappa
2019-01-29  8:10 ` [PATCHv3 22/27] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-01-30 18:49   ` Rob Herring
2019-01-29  8:10 ` [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-02-08 12:49   ` Subrahmanya Lingappa
2019-02-18  7:05     ` Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 24/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-02-08 12:52   ` Subrahmanya Lingappa
2019-02-18  7:10     ` Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 25/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou
2019-02-08 12:53   ` Subrahmanya Lingappa
2019-02-18  7:14     ` Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 26/27] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2019-01-29  8:11 ` [PATCHv3 27/27] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-01-29 11:39 ` [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Lorenzo Pieralisi
     [not found]   ` <CAFZiPx002HED+YH2GysS7a7uoEDQuHGjxa_CQtwb9nSDH-XNuA@mail.gmail.com>
2019-02-04 16:13     ` Lorenzo Pieralisi
2019-02-04 16:51       ` Subrahmanya Lingappa
2019-01-30 15:34 ` Bjorn Helgaas

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