From: "Z.q. Hou" <zhiqiang.hou@nxp.com>
To: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
Leo Li <leoyang.li@nxp.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
Mingkai Hu <mingkai.hu@nxp.com>,
"M.h. Lian" <minghuan.lian@nxp.com>,
Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: RE: [PATCHv3 09/27] PCI: mobiveil: correct inbound/outbound window setup routines
Date: Mon, 18 Feb 2019 07:07:23 +0000 [thread overview]
Message-ID: <VI1PR04MB57928B4F6F3D3A1D76B933A884630@VI1PR04MB5792.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <CAFZiPx2Qc50LpfdaBm=FYcQPmO5eB5j4SB8w-rNVs0jmJc6jqw@mail.gmail.com>
Hi Subbu,
Thanks a lot for your comments!
> -----Original Message-----
> From: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
> Sent: 2019年2月5日 14:10
> To: Z.q. Hou <zhiqiang.hou@nxp.com>
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>;
> lorenzo.pieralisi@arm.com; catalin.marinas@arm.com;
> will.deacon@arm.com; Mingkai Hu <mingkai.hu@nxp.com>; M.h. Lian
> <minghuan.lian@nxp.com>; Xiaowei Bao <xiaowei.bao@nxp.com>
> Subject: Re: [PATCHv3 09/27] PCI: mobiveil: correct inbound/outbound
> window setup routines
>
> ZQ,
> please correct the tab spacing of the macro definitions, otherwise its OK.
It is just a display issue in the email.
> Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
>
> On Tue, Jan 29, 2019 at 1:39 PM Z.q. Hou <zhiqiang.hou@nxp.com> wrote:
> >
> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> >
> > Outbound window routine:
> > - Removed unused var definition and register read operations.
> > - Added the upper 32-bit cpu address setup of the window.
> > - Instead of blindly write, only change the fields specified.
> > - Masked the lower bits of window size in case override the
> > control bits.
> > - Check if the passing window number is available, instead of
> > the total number of the initialized windows.
> >
> > Inbound window routine:
> > - Added parameter 'u64 cpu_addr' to specify the cpu address
> > of the window instead of using 'pci_addr'.
> > - Changed 'int pci_addr' to 'u64 pci_addr', and added setup
> > of the upper 32-bit pci address of the window.
> > - Moved the PCIe PIO master enablement to mobiveil_host_init().
> > - Instead of blindly write, only change the fields specified.
> > - Masked the lower bits of window size in case override the
> > control bits.
> > - Check if the passing window number is available, instead of
> > the total number of the initialized windows.
> > - And added the statistic of initialized inbound windows.
> >
> > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> > driver")
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > V3:
> > - No change
> >
> > drivers/pci/controller/pcie-mobiveil.c | 70
> > +++++++++++++++-----------
> > 1 file changed, 42 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index e88afc792a5c..4ba458474e42 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -65,9 +65,13 @@
> > #define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0,
> win)
> > #define WIN_ENABLE_SHIFT 0
> > #define WIN_TYPE_SHIFT 1
> > +#define WIN_TYPE_MASK 0x3
> > +#define WIN_SIZE_SHIFT 10
> > +#define WIN_SIZE_MASK 0x3fffff
> >
> > #define PAB_EXT_AXI_AMAP_SIZE(win)
> PAB_EXT_REG_ADDR(0xbaf0, win)
> >
> > +#define PAB_EXT_AXI_AMAP_AXI_WIN(win)
> PAB_EXT_REG_ADDR(0x80a0, win)
> > #define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4,
> win)
> > #define AXI_WINDOW_ALIGN_MASK 3
> >
> > @@ -82,8 +86,10 @@
> > #define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0,
> win)
> > #define AMAP_CTRL_EN_SHIFT 0
> > #define AMAP_CTRL_TYPE_SHIFT 1
> > +#define AMAP_CTRL_TYPE_MASK 3
> >
> > #define PAB_EXT_PEX_AMAP_SIZEN(win)
> PAB_EXT_REG_ADDR(0xbef0, win)
> > +#define PAB_EXT_PEX_AMAP_AXI_WIN(win)
> PAB_EXT_REG_ADDR(0xb4a0, win)
> > #define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4,
> win)
> > #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8,
> win)
> > #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac,
> win)
> > @@ -455,49 +461,51 @@ static int mobiveil_pcie_parse_dt(struct
> > mobiveil_pcie *pcie) }
> >
> > static void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
> > - int pci_addr, u32 type, u64 size)
> > + u64 cpu_addr, u64 pci_addr, u32
> type,
> > + u64 size)
> > {
> > - int pio_ctrl_val;
> > - int amap_ctrl_dw;
> > + u32 value;
> > u64 size64 = ~(size - 1);
> >
> > - if ((pcie->ib_wins_configured + 1) > pcie->ppio_wins) {
> > + if (win_num >= pcie->ppio_wins) {
> > dev_err(&pcie->pdev->dev,
> > "ERROR: max inbound windows
> reached !\n");
> > return;
> > }
> >
> > - pio_ctrl_val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > - pio_ctrl_val |= 1 << PIO_ENABLE_SHIFT;
> > - csr_writel(pcie, pio_ctrl_val, PAB_PEX_PIO_CTRL);
> > -
> > - amap_ctrl_dw = csr_readl(pcie,
> PAB_PEX_AMAP_CTRL(win_num));
> > - amap_ctrl_dw |= (type << AMAP_CTRL_TYPE_SHIFT) |
> > - (1 << AMAP_CTRL_EN_SHIFT) |
> > - lower_32_bits(size64);
> > - csr_writel(pcie, amap_ctrl_dw, PAB_PEX_AMAP_CTRL(win_num));
> > + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
> > + value &= ~(AMAP_CTRL_TYPE_MASK <<
> AMAP_CTRL_TYPE_SHIFT |
> > + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> > + value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 <<
> AMAP_CTRL_EN_SHIFT) |
> > + (lower_32_bits(size64) & WIN_SIZE_MASK <<
> WIN_SIZE_SHIFT);
> > + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
> >
> > csr_writel(pcie, upper_32_bits(size64),
> > PAB_EXT_PEX_AMAP_SIZEN(win_num));
> >
> > - csr_writel(pcie, pci_addr, PAB_PEX_AMAP_AXI_WIN(win_num));
> > + csr_writel(pcie, lower_32_bits(cpu_addr),
> > + PAB_PEX_AMAP_AXI_WIN(win_num));
> > + csr_writel(pcie, upper_32_bits(cpu_addr),
> > + PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
> > +
> > + csr_writel(pcie, lower_32_bits(pci_addr),
> > + PAB_PEX_AMAP_PEX_WIN_L(win_num));
> > + csr_writel(pcie, upper_32_bits(pci_addr),
> > + PAB_PEX_AMAP_PEX_WIN_H(win_num));
> >
> > - csr_writel(pcie, pci_addr,
> PAB_PEX_AMAP_PEX_WIN_L(win_num));
> > - csr_writel(pcie, 0, PAB_PEX_AMAP_PEX_WIN_H(win_num));
> > + pcie->ib_wins_configured++;
> > }
> >
> > /*
> > * routine to program the outbound windows
> > */
> > static void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
> > - u64 cpu_addr, u64 pci_addr,
> > - u32 config_io_bit, u64 size)
> > + u64 cpu_addr, u64 pci_addr, u32
> type,
> > + u64 size)
> > {
> >
> > - u32 value, type;
> > + u32 value;
> > u64 size64 = ~(size - 1);
> >
> > - if ((pcie->ob_wins_configured + 1) > pcie->apio_wins) {
> > + if (win_num >= pcie->apio_wins) {
> > dev_err(&pcie->pdev->dev,
> > "ERROR: max outbound windows
> reached !\n");
> > return;
> > @@ -507,10 +515,12 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> > * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window
> Size Bit
> > * to 4 KB in PAB_AXI_AMAP_CTRL register
> > */
> > - type = config_io_bit;
> > value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
> > - csr_writel(pcie, 1 << WIN_ENABLE_SHIFT | type <<
> WIN_TYPE_SHIFT |
> > - lower_32_bits(size64),
> PAB_AXI_AMAP_CTRL(win_num));
> > + value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
> > + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
> > + value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
> > + (lower_32_bits(size64) & WIN_SIZE_MASK <<
> WIN_SIZE_SHIFT);
> > + csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
> >
> > csr_writel(pcie, upper_32_bits(size64),
> > PAB_EXT_AXI_AMAP_SIZE(win_num));
> >
> > @@ -518,11 +528,10 @@ static void program_ob_windows(struct
> mobiveil_pcie *pcie, int win_num,
> > * program AXI window base with appropriate value in
> > * PAB_AXI_AMAP_AXI_WIN0 register
> > */
> > - value = csr_readl(pcie, PAB_AXI_AMAP_AXI_WIN(win_num));
> > - csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
> > + csr_writel(pcie, lower_32_bits(cpu_addr) &
> > + (~AXI_WINDOW_ALIGN_MASK),
> > PAB_AXI_AMAP_AXI_WIN(win_num));
> > -
> > - value = csr_readl(pcie, PAB_AXI_AMAP_PEX_WIN_H(win_num));
> > + csr_writel(pcie, upper_32_bits(cpu_addr),
> > + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
> >
> > csr_writel(pcie, lower_32_bits(pci_addr),
> > PAB_AXI_AMAP_PEX_WIN_L(win_num)); @@
> -604,6 +613,11
> > @@ static int mobiveil_host_init(struct mobiveil_pcie *pcie)
> > value |= APIO_EN_MASK;
> > csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
> >
> > + /* Enable PCIe PIO master */
> > + value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
> > + value |= 1 << PIO_ENABLE_SHIFT;
> > + csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
> > +
> > /*
> > * we'll program one outbound window for config reads and
> > * another default inbound window for all the upstream traffic
> > @@ -616,7 +630,7 @@ static int mobiveil_host_init(struct mobiveil_pcie
> *pcie)
> > CFG_WINDOW_TYPE,
> > resource_size(pcie->ob_io_res));
> >
> > /* memory inbound translation window */
> > - program_ib_windows(pcie, WIN_NUM_0, 0,
> MEM_WINDOW_TYPE, IB_WIN_SIZE);
> > + program_ib_windows(pcie, WIN_NUM_0, 0, 0,
> MEM_WINDOW_TYPE,
> > + IB_WIN_SIZE);
> >
> > /* Get the I/O and memory ranges from DT */
> > resource_list_for_each_entry(win, &pcie->resources) {
> > --
> > 2.17.1
> >
Thanks,
Zhiqiang
next prev parent reply other threads:[~2019-02-18 7:07 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-29 8:08 [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Z.q. Hou
2019-01-29 8:08 ` [PATCHv3 01/27] PCI: mobiveil: uniform the register accessors Z.q. Hou
2019-02-05 5:39 ` Subrahmanya Lingappa
2019-02-05 17:43 ` Lorenzo Pieralisi
2019-02-06 10:59 ` Subrahmanya Lingappa
2019-01-29 8:08 ` [PATCHv3 02/27] PCI: mobiveil: format the code without function change Z.q. Hou
2019-02-05 5:48 ` Subrahmanya Lingappa
2019-02-18 7:03 ` Z.q. Hou
2019-01-29 8:08 ` [PATCHv3 03/27] PCI: mobiveil: correct the returned error number Z.q. Hou
2019-02-05 5:53 ` Subrahmanya Lingappa
2019-01-29 8:08 ` [PATCHv3 04/27] PCI: mobiveil: remove flag MSI_FLAG_MULTI_PCI_MSI Z.q. Hou
2019-02-05 6:05 ` Subrahmanya Lingappa
2019-02-18 7:03 ` Z.q. Hou
2019-01-29 8:09 ` [PATCHv3 05/27] PCI: mobiveil: correct PCI base address in MEM/IO outbound windows Z.q. Hou
2019-02-05 6:06 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 06/27] PCI: mobiveil: replace the resource list iteration function Z.q. Hou
2019-02-05 6:07 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 07/27] PCI: mobiveil: use WIN_NUM_0 explicitly for CFG outbound window Z.q. Hou
2019-02-05 6:08 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 08/27] PCI: mobiveil: use the 1st inbound window for MEM inbound transactions Z.q. Hou
2019-02-05 6:08 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 09/27] PCI: mobiveil: correct inbound/outbound window setup routines Z.q. Hou
2019-02-05 6:10 ` Subrahmanya Lingappa
2019-02-18 7:07 ` Z.q. Hou [this message]
2019-01-29 8:09 ` [PATCHv3 10/27] PCI: mobiveil: fix the INTx process error Z.q. Hou
2019-02-05 6:11 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 11/27] PCI: mobiveil: only fix up the Class Code field Z.q. Hou
2019-02-05 6:11 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 12/27] PCI: mobiveil: move out the link up waiting from mobiveil_host_init Z.q. Hou
2019-02-05 6:12 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 13/27] PCI: mobiveil: move irq chained handler setup out of DT parse Z.q. Hou
2019-02-08 12:30 ` Subrahmanya Lingappa
2019-01-29 8:09 ` [PATCHv3 14/27] PCI: mobiveil: initialize Primary/Secondary/Subordinate bus number Z.q. Hou
2019-02-08 12:31 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 15/27] dt-bindings: pci: mobiveil: change gpio_slave and apb_csr to optional Z.q. Hou
2019-02-08 12:32 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 16/27] PCI: mobiveil: refactor Mobiveil PCIe Host Bridge IP driver Z.q. Hou
2019-02-08 12:37 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device Z.q. Hou
2019-02-08 12:41 ` Subrahmanya Lingappa
2019-02-08 14:13 ` Bjorn Helgaas
2019-02-18 7:15 ` Z.q. Hou
2019-02-18 7:04 ` Z.q. Hou
2019-01-29 8:10 ` [PATCHv3 18/27] PCI: mobiveil: continue to initialize the host upon no PCIe link Z.q. Hou
2019-02-08 12:41 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 19/27] PCI: mobiveil: disabled IB and OB windows set by bootloader Z.q. Hou
2019-02-08 12:42 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 20/27] PCI: mobiveil: add Byte and Half-Word width register accessors Z.q. Hou
2019-02-08 12:44 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 21/27] PCI: mobiveil: make mobiveil_host_init can be used to re-init host Z.q. Hou
2019-02-08 12:46 ` Subrahmanya Lingappa
2019-01-29 8:10 ` [PATCHv3 22/27] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller Z.q. Hou
2019-01-30 18:49 ` Rob Herring
2019-01-29 8:10 ` [PATCHv3 23/27] PCI: mobiveil: add PCIe Gen4 RC driver for NXP Layerscape SoCs Z.q. Hou
2019-02-08 12:49 ` Subrahmanya Lingappa
2019-02-18 7:05 ` Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 24/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577 Z.q. Hou
2019-02-08 12:52 ` Subrahmanya Lingappa
2019-02-18 7:10 ` Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 25/27] PCI: mobiveil: ls_pcie_g4: add Workaround for A-011451 Z.q. Hou
2019-02-08 12:53 ` Subrahmanya Lingappa
2019-02-18 7:14 ` Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 26/27] arm64: dts: freescale: lx2160a: add pcie DT nodes Z.q. Hou
2019-01-29 8:11 ` [PATCHv3 27/27] arm64: defconfig: Enable CONFIG_PCI_LAYERSCAPE_GEN4 Z.q. Hou
2019-01-29 11:39 ` [PATCHv3 00/27] PCI: refactor Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs Lorenzo Pieralisi
[not found] ` <CAFZiPx002HED+YH2GysS7a7uoEDQuHGjxa_CQtwb9nSDH-XNuA@mail.gmail.com>
2019-02-04 16:13 ` Lorenzo Pieralisi
2019-02-04 16:51 ` Subrahmanya Lingappa
2019-01-30 15:34 ` Bjorn Helgaas
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