RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops

From: Richard Zhu <hongxing.zhu@nxp.com>
To: "Z.q. Hou" <zhiqiang.hou@nxp.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
	Bjorn Helgaas <helgaas@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"robh@kernel.org" <robh@kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>
Subject: RE: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops
Date: Thu, 22 Oct 2020 06:20:18 +0000	[thread overview]
Message-ID: <VI1PR04MB5853E16DDAC5A382779F63F38C1D0@VI1PR04MB5853.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <HE1PR0402MB3371B927C5704F0C77E0EDB9841C0@HE1PR0402MB3371.eurprd04.prod.outlook.com>

> -----Original Message-----
> From: Z.q. Hou <zhiqiang.hou@nxp.com>
> Sent: Wednesday, October 21, 2020 4:48 PM
> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; Richard Zhu
> <hongxing.zhu@nxp.com>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>; Bjorn Helgaas
> <helgaas@kernel.org>; linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org;
> robh@kernel.org; bhelgaas@google.com; gustavo.pimentel@synopsys.com
> Subject: RE: [PATCH] PCI: dwc: Added link up check in map_bus of
> dw_child_pcie_ops
> 
> Hi Lorenzo and Richard,
> 
> > -----Original Message-----
> > From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Sent: 2020年10月20日 17:55
> > To: Z.q. Hou <zhiqiang.hou@nxp.com>
> > Cc: Kishon Vijay Abraham I <kishon@ti.com>; Bjorn Helgaas
> > <helgaas@kernel.org>; linux-kernel@vger.kernel.org;
> > linux-pci@vger.kernel.org; robh@kernel.org; bhelgaas@google.com;
> > gustavo.pimentel@synopsys.com
> > Subject: Re: [PATCH] PCI: dwc: Added link up check in map_bus of
> > dw_child_pcie_ops
> >
> > On Tue, Oct 20, 2020 at 02:13:13AM +0000, Z.q. Hou wrote:
> >
> > [...]
> >
> > > > > For NXP Layerscape platforms (the ls1028a and ls2088a are also
> > > > > NXP
> > > > Layerscape platform), as the error response to AXI/AHB was
> > > > enabled, it will get UR error and trigger SError on AXI bus when
> > > > it accesses a non-existent BDF on a link down bus. I'm not clear
> > > > about how it happens on dra7xxx and imx6, since they doesn't
> > > > enable the error
> > response to AXI/AHB.
> > > >
> > > > That's exactly the case with DRA7xx as the error response is
> > > > enabled by default in the platform integration.
> > >
> > > Got feedback from the imx6 owner that imx6 like the dra7xx has the
> > > error response enabled by default.  Now it's clear that the problem
> > > on all these platforms is the same.
> >
> > On IMX6, enabled by default and read-only ? Or it can be changed ?
> 
> The AXI/AHB Bridge Slave Error Response Register is a common register of DWC IP,
> so I think it should be writeable. Richard, can you help to confirm?
> 
This register is writable, but only some bits of this reg can be wrote.

Best Regards
Richard Zhu

> > What's the plan for layerscape on this matter ?
> 
> I trend to change it back to the default error response behavior so that won't
> cause any error on CFG access, and have sent out the patch.
> And for the link up check before CFG accesses, in the DWC databoot (4.40a), it
> requires link up check before generating CFG requests, so need Gustavo help to
> make sure the reason of this requirement, any potential impact without the link
> up check.
> 
> Thanks,
> Zhiqiang
> >
> > Lorenzo