From: Jean-Philippe Brucker <jean-philippe@linaro.org>
To: Robin Murphy <robin.murphy@arm.com>
Cc: joro@8bytes.org, will@kernel.org, lorenzo.pieralisi@arm.com,
robh+dt@kernel.org, guohanjun@huawei.com, sudeep.holla@arm.com,
rjw@rjwysocki.net, lenb@kernel.org, bhelgaas@google.com,
Jonathan.Cameron@huawei.com, eric.auger@redhat.com,
iommu@lists.linux-foundation.org, devicetree@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, baolu.lu@linux.intel.com,
zhangfei.gao@linaro.org, shameerali.kolothum.thodi@huawei.com,
vivek.gautam@arm.com
Subject: Re: [PATCH v8 4/9] of/iommu: Support dma-can-stall property
Date: Mon, 14 Dec 2020 13:51:41 +0100 [thread overview]
Message-ID: <X9dS9H9PrOZbND9E@myrica> (raw)
In-Reply-To: <d0a61d79-82fc-3af8-570e-e2ae3d485455@arm.com>
On Thu, Nov 26, 2020 at 06:09:26PM +0000, Robin Murphy wrote:
> On 2020-11-12 12:55, Jean-Philippe Brucker wrote:
> > Copy the dma-can-stall property into the fwspec structure.
>
> Can't we just handle this as a regular device property? It's not part of the
> actual IOMMU specifier, it doesn't need to be translated in any way, and
> AFAICS it's used a grand total of once, in a slow path. Simply treating it
> as the per-device property that it is should require zero additional code
> for DT, and a simple device_add_properties() call for IORT.
>
> TBH that appears to be true of pasid-num-bits as well.
Right I think that's better, thanks for the pointer. I'll take care of
pasid-num-bits too. The Huawei quirk (fake PCIe supporting stall) is a
little worse this way, but it should work.
Thanks,
Jean
---
Diff untested on ACPI:
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index e7b40e569488..ad5c55bc45b2 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -591,8 +591,6 @@ struct iommu_group *fsl_mc_device_group(struct device *dev);
struct iommu_fwspec {
const struct iommu_ops *ops;
struct fwnode_handle *iommu_fwnode;
- u32 num_pasid_bits;
- bool can_stall;
unsigned int num_ids;
u32 ids[];
};
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index aa76e775bd6d..1582f6585741 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -960,16 +960,19 @@ static int iort_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data)
static void iort_named_component_init(struct device *dev,
struct acpi_iort_node *node)
{
+ struct property_entry props[3] = {};
struct acpi_iort_named_component *nc;
- struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
-
- if (!fwspec)
- return;
nc = (struct acpi_iort_named_component *)node->node_data;
- fwspec->num_pasid_bits = FIELD_GET(ACPI_IORT_NC_PASID_BITS,
- nc->node_flags);
- fwspec->can_stall = (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED);
+
+ props[0] = PROPERTY_ENTRY_U32("pasid-num-bits",
+ FIELD_GET(ACPI_IORT_NC_PASID_BITS,
+ nc->node_flags));
+ if (nc->node_flags & ACPI_IORT_NC_STALL_SUPPORTED)
+ props[1] = PROPERTY_ENTRY_BOOL("dma-can-stall");
+
+ if (device_add_properties(dev, props))
+ dev_warn(dev, "Could not register device properties\n");
}
static int iort_nc_iommu_map(struct device *dev, struct acpi_iort_node *node)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 521ec7f0b2a0..571bd7c35a62 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -2842,7 +2842,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev)
if (ret)
goto err_free_master;
- master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits);
+ device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits);
+ master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits);
/*
* Note that PASID must be enabled before, and disabled after ATS:
@@ -2858,7 +2859,8 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev)
master->ssid_bits = min_t(u8, master->ssid_bits,
CTXDESC_LINEAR_CDMAX);
- if ((smmu->features & ARM_SMMU_FEAT_STALLS && fwspec->can_stall) ||
+ if ((smmu->features & ARM_SMMU_FEAT_STALLS &&
+ device_property_read_bool(dev, "dma-can-stall")) ||
smmu->features & ARM_SMMU_FEAT_STALL_FORCE)
master->stall_enabled = true;
diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c
index d6255ca823d8..a9d2df001149 100644
--- a/drivers/iommu/of_iommu.c
+++ b/drivers/iommu/of_iommu.c
@@ -210,14 +210,6 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,
of_pci_iommu_init, &info);
} else {
err = of_iommu_configure_device(master_np, dev, id);
-
- fwspec = dev_iommu_fwspec_get(dev);
- if (!err && fwspec) {
- of_property_read_u32(master_np, "pasid-num-bits",
- &fwspec->num_pasid_bits);
- fwspec->can_stall = of_property_read_bool(master_np,
- "dma-can-stall");
- }
}
/*
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 324dbe55836c..13a43a3d6347 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -1828,12 +1828,17 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI
static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
{
- struct iommu_fwspec *fwspec;
+ struct property_entry properties[] = {
+ PROPERTY_ENTRY_BOOL("dma-can-stall"),
+ {},
+ };
pdev->eetlp_prefix_path = 1;
- fwspec = dev_iommu_fwspec_get(&pdev->dev);
- if (fwspec)
- fwspec->can_stall = 1;
+
+ /* Device-tree can set the stall property */
+ if (!pdev->dev.of_node &&
+ device_add_properties(&pdev->dev, properties))
+ pci_warn(pdev, "could not add stall property");
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
next prev parent reply other threads:[~2020-12-14 12:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-12 12:55 [PATCH v8 0/9] iommu: I/O page faults for SMMUv3 Jean-Philippe Brucker
2020-11-12 12:55 ` [PATCH v8 1/9] iommu: Add a page fault handler Jean-Philippe Brucker
2020-11-12 12:55 ` [PATCH v8 2/9] iommu/arm-smmu-v3: Maintain a SID->device structure Jean-Philippe Brucker
2020-11-12 12:55 ` [PATCH v8 3/9] dt-bindings: document stall property for IOMMU masters Jean-Philippe Brucker
2020-11-12 12:55 ` [PATCH v8 4/9] of/iommu: Support dma-can-stall property Jean-Philippe Brucker
2020-11-26 18:09 ` Robin Murphy
2020-12-14 12:51 ` Jean-Philippe Brucker [this message]
2020-12-18 6:47 ` Zhangfei Gao
2020-11-12 12:55 ` [PATCH v8 5/9] ACPI/IORT: Enable stall support for platform devices Jean-Philippe Brucker
2020-11-13 0:41 ` Hanjun Guo
2020-11-12 12:55 ` [PATCH v8 6/9] iommu/arm-smmu-v3: Add " Jean-Philippe Brucker
2020-11-12 12:55 ` [PATCH v8 7/9] PCI/ATS: Add PRI stubs Jean-Philippe Brucker
2020-11-12 12:55 ` [PATCH v8 8/9] PCI/ATS: Export PRI functions Jean-Philippe Brucker
2020-11-12 12:55 ` [PATCH v8 9/9] iommu/arm-smmu-v3: Add support for PRI Jean-Philippe Brucker
2020-12-03 6:52 ` [PATCH v8 0/9] iommu: I/O page faults for SMMUv3 Vivek Gautam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=X9dS9H9PrOZbND9E@myrica \
--to=jean-philippe@linaro.org \
--cc=Jonathan.Cameron@huawei.com \
--cc=baolu.lu@linux.intel.com \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=eric.auger@redhat.com \
--cc=guohanjun@huawei.com \
--cc=iommu@lists.linux-foundation.org \
--cc=joro@8bytes.org \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=rjw@rjwysocki.net \
--cc=robh+dt@kernel.org \
--cc=robin.murphy@arm.com \
--cc=shameerali.kolothum.thodi@huawei.com \
--cc=sudeep.holla@arm.com \
--cc=vivek.gautam@arm.com \
--cc=will@kernel.org \
--cc=zhangfei.gao@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).