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Mon, 23 Jan 2023 02:44:38 -0800 (PST) Received: from linaro.org ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id k9-20020a5d6d49000000b002bc8130cca7sm34107744wri.23.2023.01.23.02.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 02:44:38 -0800 (PST) Date: Mon, 23 Jan 2023 12:44:36 +0200 From: Abel Vesa To: Krzysztof Kozlowski Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: Re: [PATCH v4 09/12] dt-bindings: PCI: qcom: Add SM8550 compatible Message-ID: References: <20230119140453.3942340-1-abel.vesa@linaro.org> <20230119140453.3942340-10-abel.vesa@linaro.org> <7af21247-a44e-cb46-7461-204fa6b4fcab@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7af21247-a44e-cb46-7461-204fa6b4fcab@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 23-01-22 15:10:59, Krzysztof Kozlowski wrote: > On 19/01/2023 15:04, Abel Vesa wrote: > > Add the SM8550 platform to the binding. > > > > Signed-off-by: Abel Vesa > > --- > > > > The v3 of this patchset is: > > https://lore.kernel.org/all/20230119112453.3393911-1-abel.vesa@linaro.org/ > > > > Changes since v3: > > * renamed noc_aggr to noc_aggr_4, as found in the driver > > > > Changes since v2: > > * dropped the pipe from clock-names > > * removed the pcie instance number from aggre clock-names comment > > * renamed aggre clock-names to noc_aggr > > * dropped the _pcie infix from cnoc_pcie_sf_axi > > * renamed pcie_1_link_down_reset to simply link_down > > * added enable-gpios back, since pcie1 node will use it > > > > Changes since v1: > > * Switched to single compatible for both PCIes (qcom,pcie-sm8550) > > * dropped enable-gpios property > > * dropped interconnects related properties, the power-domains > > * properties > > and resets related properties the sm8550 specific allOf:if:then > > * dropped pipe_mux, phy_pipe and ref clocks from the sm8550 specific > > allOf:if:then clock-names array and decreased the minItems and > > maxItems for clocks property accordingly > > * added "minItems: 1" to interconnects, since sm8550 pcie uses just > > * one, > > same for interconnect-names > > > > > > .../devicetree/bindings/pci/qcom,pcie.yaml | 44 +++++++++++++++++++ > > 1 file changed, 44 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > index a5859bb3dc28..58f926666332 100644 > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > > @@ -34,6 +34,7 @@ properties: > > - qcom,pcie-sm8250 > > - qcom,pcie-sm8450-pcie0 > > - qcom,pcie-sm8450-pcie1 > > + - qcom,pcie-sm8550 > > - qcom,pcie-ipq6018 > > > > reg: > > @@ -65,9 +66,11 @@ properties: > > dma-coherent: true > > > > interconnects: > > + minItems: 1 > > maxItems: 2 > > > > I don't see my concerns from v3 answered. Check the dates for v4 and your reply to v3. v4 was sent a day before you sent your v3 comments. :) > > This is a friendly reminder during the review process. > > It seems my previous comments were not fully addressed. Maybe my > feedback got lost between the quotes, maybe you just forgot to apply it. > Please go back to the previous discussion and either implement all > requested changes or keep discussing them. Will address your comments in next version. > > Thank you. > > Best regards, > Krzysztof >