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From: "Krzysztof Wilczyński" <kw@linux.com>
To: srikanth.thokala@intel.com
Cc: bhelgaas@google.com, robh+dt@kernel.org,
	lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, andriy.shevchenko@linux.intel.com,
	mgross@linux.intel.com, lakshmi.bai.raja.subramanian@intel.com,
	mallikarjunappa.sangannavar@intel.com
Subject: Re: [PATCH v7 2/2] PCI: keembay: Add support for Intel Keem Bay
Date: Wed, 10 Feb 2021 01:36:21 +0100	[thread overview]
Message-ID: <YCMqhe4w1QFYoGhE@rocinante> (raw)
In-Reply-To: <20210124234702.21074-3-srikanth.thokala@intel.com>

Hi Srikanth,

Thank you for all the work here!

> +config PCIE_KEEMBAY_HOST
> +	bool "Intel Keem Bay PCIe controller - Host mode"
> +	depends on ARCH_KEEMBAY || COMPILE_TEST
> +	depends on PCI && PCI_MSI_IRQ_DOMAIN
> +	select PCIE_DW_HOST
> +	select PCIE_KEEMBAY
> +	help
> +	  Say 'Y' here to enable support for the PCIe controller in Keem Bay
> +	  to work in host mode.
> +	  The PCIe controller is based on Designware Hardware and uses
> +	  DesignWare core functions.
> +
> +config PCIE_KEEMBAY_EP
> +	bool "Intel Keem Bay PCIe controller - Endpoint mode"
> +	depends on ARCH_KEEMBAY || COMPILE_TEST
> +	depends on PCI && PCI_MSI_IRQ_DOMAIN
> +	depends on PCI_ENDPOINT
> +	select PCIE_DW_EP
> +	select PCIE_KEEMBAY
> +	help
> +	  Say 'Y' here to enable support for the PCIe controller in Keem Bay
> +	  to work in endpoint mode.
> +	  The PCIe controller is based on Designware Hardware and uses
> +	  DesignWare core functions.

It would be "DesignWare" in the sentences above.

[...]
> +static void keembay_ep_reset_deassert(struct keembay_pcie *pcie)
> +{
> +	/*
> +	 * Ensure that PERST# is asserted for a minimum of 100ms
[...]

Just a nitpick, so feel free to ignore, absolutely.  A missing period at
the end of the sentence.

> +static void keembay_pcie_ltssm_enable(struct keembay_pcie *pcie, bool enable)
> +{
> +	u32 val;
> +
> +	val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL);
> +	if (enable)
> +		val |= APP_LTSSM_ENABLE;
> +	else
> +		val &= ~APP_LTSSM_ENABLE;
> +	writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL);
> +}
>

Another nitpick, so also feel free to ignore, of course.

I wonder if calling this function keembay_pcie_set_ltssm or perhaps
keembay_pcie_ltssm_set would be more aligned with what it does, since it
turns the LTSSM support on and off, so to speak, as needed.  Do you
think this would be OK to do?

Krzysztof

      parent reply	other threads:[~2021-02-10  0:39 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-24 23:47 [PATCH v7 0/2] " srikanth.thokala
2021-01-24 23:47 ` [PATCH v7 1/2] dt-bindings: PCI: Add Intel Keem Bay PCIe controller srikanth.thokala
2021-02-10  0:42   ` Krzysztof Wilczyński
2021-02-17  6:03     ` Thokala, Srikanth
2021-01-24 23:47 ` [PATCH v7 2/2] PCI: keembay: Add support for Intel Keem Bay srikanth.thokala
2021-02-09 19:01   ` Thokala, Srikanth
2021-02-10  0:36   ` Krzysztof Wilczyński [this message]

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