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* [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI
@ 2021-02-09 10:19 Bharat Kumar Gogada
  2021-02-09 10:19 ` [PATCH 2/2] PCI: xilinx-nwl: Add optional "dma-coherent" property Bharat Kumar Gogada
  2021-02-10 21:45 ` [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Krzysztof Wilczyński
  0 siblings, 2 replies; 4+ messages in thread
From: Bharat Kumar Gogada @ 2021-02-09 10:19 UTC (permalink / raw)
  To: linux-pci, linux-kernel; +Cc: bhelgaas, Bharat Kumar Gogada

Add support for routing PCIe DMA traffic coherently when
Cache Coherent Interconnect (CCI) is enabled in the system.
The "dma-coherent" property is used to determine if CCI is enabled
or not.
Refer https://developer.arm.com/documentation/ddi0470/k/preface
for CCI specification.

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
 drivers/pci/controller/pcie-xilinx-nwl.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 07e36661bbc2..08e060574cb7 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -26,6 +26,7 @@
 
 /* Bridge core config registers */
 #define BRCFG_PCIE_RX0			0x00000000
+#define BRCFG_PCIE_RX1			0x00000004
 #define BRCFG_INTERRUPT			0x00000010
 #define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
 
@@ -128,6 +129,7 @@
 #define NWL_ECAM_VALUE_DEFAULT		12
 
 #define CFG_DMA_REG_BAR			GENMASK(2, 0)
+#define CFG_PCIE_CACHE			GENMASK(7, 0)
 
 #define INT_PCI_MSI_NR			(2 * 32)
 
@@ -675,6 +677,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
 	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
 			  BRCFG_PCIE_RX_MSG_FILTER);
 
+	/* This routes the PCIe DMA traffic to go through CCI path */
+	if (of_dma_is_coherent(dev->of_node)) {
+		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
+				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
+	}
+
 	err = nwl_wait_for_link(pcie);
 	if (err)
 		return err;
-- 
2.17.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 2/2] PCI: xilinx-nwl: Add optional "dma-coherent" property
  2021-02-09 10:19 [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Bharat Kumar Gogada
@ 2021-02-09 10:19 ` Bharat Kumar Gogada
  2021-02-10 21:45 ` [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Krzysztof Wilczyński
  1 sibling, 0 replies; 4+ messages in thread
From: Bharat Kumar Gogada @ 2021-02-09 10:19 UTC (permalink / raw)
  To: linux-pci, linux-kernel; +Cc: bhelgaas, Bharat Kumar Gogada

Add optional dma-coherent property to support coherent PCIe DMA traffic.

Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
index 01bf7fdf4c19..2d677e90a7e2 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
@@ -33,6 +33,8 @@ Required properties:
 	- #address-cells: specifies the number of cells needed to encode an
 		address. The value must be 0.
 
+Optional properties:
+- dma-coherent: present if DMA operations are coherent
 
 Example:
 ++++++++
-- 
2.17.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI
  2021-02-09 10:19 [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Bharat Kumar Gogada
  2021-02-09 10:19 ` [PATCH 2/2] PCI: xilinx-nwl: Add optional "dma-coherent" property Bharat Kumar Gogada
@ 2021-02-10 21:45 ` Krzysztof Wilczyński
  2021-02-18  9:58   ` Bharat Kumar Gogada
  1 sibling, 1 reply; 4+ messages in thread
From: Krzysztof Wilczyński @ 2021-02-10 21:45 UTC (permalink / raw)
  To: Bharat Kumar Gogada; +Cc: linux-pci, linux-kernel, bhelgaas

Hi Bharat,

Thank you for sending the patches over!

> Add support for routing PCIe DMA traffic coherently when
> Cache Coherent Interconnect (CCI) is enabled in the system.
> The "dma-coherent" property is used to determine if CCI is enabled
> or not.
> Refer https://developer.arm.com/documentation/ddi0470/k/preface
> for CCI specification.
[...]

A small nitpick, so feel free to ignore, of course.

Perhaps "Refer to" and "for the CCI", etc.

[...]
> +	/* This routes the PCIe DMA traffic to go through CCI path */
> +	if (of_dma_is_coherent(dev->of_node)) {
> +		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
> +				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
> +	}
[...]

A suggestion.

You can drop the curly brackets here if you want to keep the style used
in the kernel, especially for when there is a single statement inside
the code block.

Krzysztof

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI
  2021-02-10 21:45 ` [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Krzysztof Wilczyński
@ 2021-02-18  9:58   ` Bharat Kumar Gogada
  0 siblings, 0 replies; 4+ messages in thread
From: Bharat Kumar Gogada @ 2021-02-18  9:58 UTC (permalink / raw)
  To: Krzysztof Wilczyński; +Cc: linux-pci, linux-kernel, bhelgaas

> Hi Bharat,
> 
> Thank you for sending the patches over!
> 
> > Add support for routing PCIe DMA traffic coherently when Cache
> > Coherent Interconnect (CCI) is enabled in the system.
> > The "dma-coherent" property is used to determine if CCI is enabled or
> > not.
> > Refer https://developer.arm.com/documentation/ddi0470/k/preface
> > for CCI specification.
> [...]
> 
> A small nitpick, so feel free to ignore, of course.
> 
> Perhaps "Refer to" and "for the CCI", etc.
> 
> [...]
> > +	/* This routes the PCIe DMA traffic to go through CCI path */
> > +	if (of_dma_is_coherent(dev->of_node)) {
> > +		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,
> BRCFG_PCIE_RX1) |
> > +				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
> > +	}
> [...]
> 
> A suggestion.
> 
> You can drop the curly brackets here if you want to keep the style used in
> the kernel, especially for when there is a single statement inside the code
> block.
> 
Thanks Krzysztof. Will remove it.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-02-18 12:14 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-02-09 10:19 [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Bharat Kumar Gogada
2021-02-09 10:19 ` [PATCH 2/2] PCI: xilinx-nwl: Add optional "dma-coherent" property Bharat Kumar Gogada
2021-02-10 21:45 ` [PATCH 1/2] PCI: xilinx-nwl: Enable coherent PCIe DMA traffic using CCI Krzysztof Wilczyński
2021-02-18  9:58   ` Bharat Kumar Gogada

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