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[66.111.4.228]) by smtp.gmail.com with ESMTPSA id h1sm6841841ioz.22.2021.07.20.08.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 08:01:40 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailauth.nyi.internal (Postfix) with ESMTP id 4359027C005C; Tue, 20 Jul 2021 11:01:38 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute5.internal (MEProxy); Tue, 20 Jul 2021 11:01:39 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrfedvgdekudcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpeffhffvuffkfhggtggujgesthdtredttddtvdenucfhrhhomhepuehoqhhunhcu hfgvnhhguceosghoqhhunhdrfhgvnhhgsehgmhgrihhlrdgtohhmqeenucggtffrrghtth gvrhhnpedvleeigedugfegveejhfejveeuveeiteejieekvdfgjeefudehfefhgfegvdeg jeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegsoh hquhhnodhmvghsmhhtphgruhhthhhpvghrshhonhgrlhhithihqdeiledvgeehtdeigedq udejjeekheehhedvqdgsohhquhhnrdhfvghngheppehgmhgrihhlrdgtohhmsehfihigmh gvrdhnrghmvg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 20 Jul 2021 11:01:37 -0400 (EDT) Date: Tue, 20 Jul 2021 22:59:41 +0800 From: Boqun Feng To: Marc Zyngier Cc: Bjorn Helgaas , Arnd Bergmann , Catalin Marinas , Will Deacon , "K. Y. Srinivasan" , Haiyang Zhang , Stephen Hemminger , Wei Liu , Dexuan Cui , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-hyperv@vger.kernel.org, linux-pci@vger.kernel.org, Sunil Muthuswamy , Mike Rapoport Subject: Re: [RFC v5 8/8] PCI: hv: Turn on the host bridge probing on ARM64 Message-ID: References: <20210720134429.511541-1-boqun.feng@gmail.com> <20210720134429.511541-9-boqun.feng@gmail.com> <87v95582zh.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87v95582zh.wl-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Jul 20, 2021 at 03:38:26PM +0100, Marc Zyngier wrote: > On Tue, 20 Jul 2021 14:44:29 +0100, > Boqun Feng wrote: > > > > Now we have everything we need, just provide a proper sysdata type for > > the bus to use on ARM64 and everything else works. > > > > Signed-off-by: Boqun Feng > > --- > > drivers/pci/controller/pci-hyperv.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c > > index e6276aaa4659..62dbe98d1fe1 100644 > > --- a/drivers/pci/controller/pci-hyperv.c > > +++ b/drivers/pci/controller/pci-hyperv.c > > @@ -40,6 +40,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -448,7 +449,11 @@ enum hv_pcibus_state { > > }; > > > > struct hv_pcibus_device { > > +#ifdef CONFIG_X86 > > struct pci_sysdata sysdata; > > +#elif defined(CONFIG_ARM64) > > + struct pci_config_window sysdata; > > +#endif > > Am I the only one who find this rather odd? Nothing ever populates > this data structure on arm64, and its only purpose seems to serve as > an anchor to retrieve the hbus via container_of(). > This field will also be used as the ->sysdata of pci_bus and pci_host_bridge, and some of the PCI core code touches. Although I made this field as all zeroed and make sure PCI core can handle (patch #4). > If that's indeed the case, I'd rather see an arch-specific to_hbus() > helper that uses another (preexisting) field as the anchor for arm64. > I did a quick look, but I didn't find another field works: the field needs to be placed inside hv_pcibus_device and the address can be retrieved via pci_bus. I'm open to any suggestion in case that I missed something. Regards, Boqun > Thanks, > > M. > > -- > Without deviation from the norm, progress is not possible.