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Thu, 03 Feb 2022 09:09:49 -0800 (PST) Received: from ripper ([2600:1700:a0:3dc8:205:1bff:fec0:b9b3]) by smtp.gmail.com with ESMTPSA id z4sm14340958ota.7.2022.02.03.09.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Feb 2022 09:09:49 -0800 (PST) Date: Thu, 3 Feb 2022 09:10:06 -0800 From: Bjorn Andersson To: Dmitry Baryshkov Cc: Andy Gross , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi , Bjorn Helgaas , Krzysztof Wilczy??ski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v5 5/5] PCI: qcom: Add SM8450 PCIe support Message-ID: References: <20211218141024.500952-1-dmitry.baryshkov@linaro.org> <20211218141024.500952-6-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211218141024.500952-6-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sat 18 Dec 06:10 PST 2021, Dmitry Baryshkov wrote: > On SM8450 platform PCIe hosts do not use all the clocks (and add several > additional clocks), so expand the driver to handle these requirements. > > PCIe0 and PCIe1 hosts use different sets of clocks, so separate entries > are required. > Reviewed-by: Bjorn Andersson Regards, Bjorn > Signed-off-by: Dmitry Baryshkov > --- > drivers/pci/controller/dwc/pcie-qcom.c | 57 ++++++++++++++++++++------ > 1 file changed, 44 insertions(+), 13 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 55ac3caa6d7d..fe6ed1e0415a 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -161,7 +161,7 @@ struct qcom_pcie_resources_2_3_3 { > > /* 6 clocks typically, 7 for sm8250 */ > struct qcom_pcie_resources_2_7_0 { > - struct clk_bulk_data clks[7]; > + struct clk_bulk_data clks[9]; > int num_clks; > struct regulator_bulk_data supplies[2]; > struct reset_control *pci_reset; > @@ -193,7 +193,10 @@ struct qcom_pcie_ops { > struct qcom_pcie_cfg { > const struct qcom_pcie_ops *ops; > unsigned int pipe_clk_need_muxing:1; > + unsigned int has_tbu_clk:1; > unsigned int has_ddrss_sf_tbu_clk:1; > + unsigned int has_aggre0_clk:1; > + unsigned int has_aggre1_clk:1; > }; > > struct qcom_pcie { > @@ -1117,6 +1120,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; > struct dw_pcie *pci = pcie->pci; > struct device *dev = pci->dev; > + unsigned int idx; > int ret; > > res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); > @@ -1134,18 +1138,22 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > if (ret) > return ret; > > - res->clks[0].id = "aux"; > - res->clks[1].id = "cfg"; > - res->clks[2].id = "bus_master"; > - res->clks[3].id = "bus_slave"; > - res->clks[4].id = "slave_q2a"; > - res->clks[5].id = "tbu"; > - if (pcie->cfg->has_ddrss_sf_tbu_clk) { > - res->clks[6].id = "ddrss_sf_tbu"; > - res->num_clks = 7; > - } else { > - res->num_clks = 6; > - } > + idx = 0; > + res->clks[idx++].id = "aux"; > + res->clks[idx++].id = "cfg"; > + res->clks[idx++].id = "bus_master"; > + res->clks[idx++].id = "bus_slave"; > + res->clks[idx++].id = "slave_q2a"; > + if (pcie->cfg->has_tbu_clk) > + res->clks[idx++].id = "tbu"; > + if (pcie->cfg->has_ddrss_sf_tbu_clk) > + res->clks[idx++].id = "ddrss_sf_tbu"; > + if (pcie->cfg->has_aggre0_clk) > + res->clks[idx++].id = "aggre0"; > + if (pcie->cfg->has_aggre1_clk) > + res->clks[idx++].id = "aggre1"; > + > + res->num_clks = idx; > > ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); > if (ret < 0) > @@ -1210,6 +1218,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > goto err_disable_clocks; > } > > + /* Wait for reset to complete, required on SM8450 */ > + usleep_range(1000, 1500); > + > /* configure PCIe to RC mode */ > writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); > > @@ -1457,15 +1468,33 @@ static const struct qcom_pcie_cfg ipq4019_cfg = { > > static const struct qcom_pcie_cfg sdm845_cfg = { > .ops = &ops_2_7_0, > + .has_tbu_clk = true, > }; > > static const struct qcom_pcie_cfg sm8250_cfg = { > + .ops = &ops_1_9_0, > + .has_tbu_clk = true, > + .has_ddrss_sf_tbu_clk = true, > +}; > + > +static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { > .ops = &ops_1_9_0, > .has_ddrss_sf_tbu_clk = true, > + .pipe_clk_need_muxing = true, > + .has_aggre0_clk = true, > + .has_aggre1_clk = true, > +}; > + > +static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { > + .ops = &ops_1_9_0, > + .has_ddrss_sf_tbu_clk = true, > + .pipe_clk_need_muxing = true, > + .has_aggre1_clk = true, > }; > > static const struct qcom_pcie_cfg sc7280_cfg = { > .ops = &ops_1_9_0, > + .has_tbu_clk = true, > .pipe_clk_need_muxing = true, > }; > > @@ -1564,6 +1593,8 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg }, > { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg }, > { .compatible = "qcom,pcie-sc8180x", .data = &sm8250_cfg }, > + { .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg }, > + { .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg }, > { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg }, > { } > }; > -- > 2.34.1 >