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Sun, 13 Mar 2022 10:08:16 -0700 (PDT) Received: from builder.lan ([2600:1700:a0:3dc8:3697:f6ff:fe85:aac9]) by smtp.gmail.com with ESMTPSA id w22-20020acaad16000000b002d9c98e551bsm2897103oie.36.2022.03.13.10.08.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Mar 2022 10:08:15 -0700 (PDT) Date: Sun, 13 Mar 2022 12:08:14 -0500 From: Bjorn Andersson To: Dmitry Baryshkov Cc: Andy Gross , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , Krzysztof Wilczy??ski , Bjorn Helgaas , Prasad Malisetty , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [RFC PATCH 3/5] clk: qcom: gcc-sc7280: use new clk_regmap_mux_safe_ops for PCIe pipe clocks Message-ID: References: <20220313000824.229405-1-dmitry.baryshkov@linaro.org> <20220313000824.229405-4-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220313000824.229405-4-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Sat 12 Mar 18:08 CST 2022, Dmitry Baryshkov wrote: > Use newly defined clk_regmap_mux_safe_ops for PCIe pipe clocks to let > the clock framework automatically park the clock when the clock is > switched off and restore the parent when the clock is switched on. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/clk/qcom/gcc-sc7280.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c > index 423627d49719..69887e45d02f 100644 > --- a/drivers/clk/qcom/gcc-sc7280.c > +++ b/drivers/clk/qcom/gcc-sc7280.c > @@ -373,13 +373,14 @@ static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = { > .reg = 0x6b054, > .shift = 0, > .width = 2, > + .safe_src_index = 2, > .parent_map = gcc_parent_map_6, > .clkr = { > .hw.init = &(struct clk_init_data){ > .name = "gcc_pcie_0_pipe_clk_src", > .parent_data = gcc_parent_data_6, > .num_parents = ARRAY_SIZE(gcc_parent_data_6), > - .ops = &clk_regmap_mux_closest_ops, > + .ops = &clk_regmap_mux_safe_ops, > }, > }, > }; > @@ -388,13 +389,14 @@ static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = { > .reg = 0x8d054, > .shift = 0, > .width = 2, > + .safe_src_index = 2, > .parent_map = gcc_parent_map_7, > .clkr = { > .hw.init = &(struct clk_init_data){ > .name = "gcc_pcie_1_pipe_clk_src", > .parent_data = gcc_parent_data_7, > .num_parents = ARRAY_SIZE(gcc_parent_data_7), > - .ops = &clk_regmap_mux_closest_ops, > + .ops = &clk_regmap_mux_safe_ops, > }, > }, > }; > -- > 2.34.1 >