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From: Rob Herring <robh@kernel.org>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
	"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Serge Semin" <fancer.lancer@gmail.com>,
	"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
	"Pavel Parkhomenko" <Pavel.Parkhomenko@baikalelectronics.ru>,
	"Frank Li" <Frank.Li@nxp.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 03/16] PCI: dwc: Add more verbose link-up message
Date: Tue, 29 Mar 2022 09:47:02 -0500	[thread overview]
Message-ID: <YkMb5lT91ZveLTgg@robh.at.kernel.org> (raw)
In-Reply-To: <20220324013734.18234-4-Sergey.Semin@baikalelectronics.ru>

On Thu, Mar 24, 2022 at 04:37:21AM +0300, Serge Semin wrote:
> Printing just "link up" isn't that much informative especially when it
> comes to working with the PCI Express bus. Even if the link is up, due to
> multiple reasons the bus performance can degrade to slower speeds or to
> narrower width than both Root Port and its partner is capable of. In that
> case it would be handy to know the link specifications as early as
> possible. So let's add a more verbose message to the busy-wait link-state
> method, which will contain the link speed generation and the PCIe bus
> width in case if the link up state is discovered. Otherwise an error will
> be printed to the system log.
> 
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 22 +++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 6e81264fdfb4..f1693e25afcb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -528,14 +528,26 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
>  
>  	/* Check if the link is up or not */
>  	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
> -		if (dw_pcie_link_up(pci)) {
> -			dev_info(pci->dev, "Link up\n");
> -			return 0;
> -		}
> +		if (dw_pcie_link_up(pci))
> +			break;
> +
>  		usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
>  	}
>  
> -	dev_info(pci->dev, "Phy link never came up\n");
> +	if (retries < LINK_WAIT_MAX_RETRIES) {
> +		u32 offset, val;
> +
> +		offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> +		val = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
> +
> +		dev_info(pci->dev, "PCIe Gen.%u x%u link up\n",
> +			 FIELD_GET(PCI_EXP_LNKSTA_CLS, val),
> +			 FIELD_GET(PCI_EXP_LNKSTA_NLW, val));

Given these are standard registers can we do this in the core code? The 
main issue I think is that the config space accessors don't work until 
you create the bus struct. That still should be early enough.

I think it is possible some implementations don't report the link state 
in these registers. Maybe we don't really need to care.

Rob

  parent reply	other threads:[~2022-03-29 14:47 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-24  1:37 [PATCH 00/16] PCI: dwc: Add dma-ranges/YAML-schema/Baikal-T1 support Serge Semin
2022-03-24  1:37 ` [PATCH 01/16] dt-bindings: PCI: dwc: Define generic and native DT bindings Serge Semin
2022-03-28 20:46   ` Rob Herring
2022-04-15 16:14     ` Serge Semin
2022-03-24  1:37 ` [PATCH 02/16] dt-bindings: PCI: dwc: Add Baikal-T1 PCIe Root Port bindings Serge Semin
2022-03-28 23:20   ` Rob Herring
2022-04-15 20:22     ` Serge Semin
2022-03-24  1:37 ` [PATCH 03/16] PCI: dwc: Add more verbose link-up message Serge Semin
2022-03-28 23:31   ` Joe Perches
2022-04-16  8:01     ` Serge Semin
2022-03-29 14:47   ` Rob Herring [this message]
2022-04-17 10:10     ` Serge Semin
2022-03-24  1:37 ` [PATCH 04/16] PCI: dwc: Convert to using native IP-core versions representation Serge Semin
2022-03-29 15:00   ` Rob Herring
2022-04-17 14:42     ` Serge Semin
2022-03-24  1:37 ` [PATCH 05/16] PCI: dwc: Add IP-core version detection procedure Serge Semin
2022-03-29 15:08   ` Rob Herring
2022-04-17 15:13     ` Serge Semin
2022-03-24  1:37 ` [PATCH 06/16] PCI: dwc: Introduce Synopsys IP-core versions/types interface Serge Semin
2022-03-24  1:37 ` [PATCH 07/16] PCI: dwc: Add host de-initialization callback Serge Semin
2022-03-24  1:37 ` [PATCH 08/16] PCI: dwc: Drop inbound iATU types enumeration - dw_pcie_as_type Serge Semin
2022-03-29 15:16   ` Rob Herring
2022-03-24  1:37 ` [PATCH 09/16] PCI: dwc: Simplify in/outbound iATU setup methods Serge Semin
2022-03-29 15:28   ` Rob Herring
2022-04-17 20:08     ` Serge Semin
2022-03-24  1:37 ` [PATCH 10/16] PCI: dwc: Drop iATU regions enumeration - dw_pcie_region_type Serge Semin
2022-03-29 15:31   ` Rob Herring
2022-04-17 17:52     ` Serge Semin
2022-03-24  1:37 ` [PATCH 11/16] PCI: dwc: Add iATU regions size detection procedure Serge Semin
2022-03-24  1:37 ` [PATCH 12/16] PCI: dwc: Verify in/out regions against iATU constraints Serge Semin
2022-03-24  1:37 ` [PATCH 13/16] PCI: dwc: Check iATU in/outbound ranges setup methods status Serge Semin
2022-03-24  1:37 ` [PATCH 14/16] PCI: dwc: Introduce dma-ranges property support for RC-host Serge Semin
2022-03-24  1:37 ` [PATCH 15/16] PCI: dwc: Introduce generic platform clocks and resets sets Serge Semin
2022-03-24  1:37 ` [PATCH 16/16] PCI: dwc: Add Baikal-T1 PCIe controller support Serge Semin

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