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Date:   Fri, 13 May 2022 14:57:02 +0200
From:   Johan Hovold <johan@kernel.org>
To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzk@kernel.org>,
        Jingoo Han <jingoohan1@gmail.com>,
        Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Stanimir Varbanov <svarbanov@mm-sol.com>,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        Vinod Koul <vkoul@kernel.org>, linux-arm-msm@vger.kernel.org,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v8 07/10] PCI: qcom: Handle MSIs routed to multiple GIC
 interrupts
Message-ID: <Yn5Vnnp7NynOl1DU@hovoldconsulting.com>
References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org>
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On Fri, May 13, 2022 at 03:48:09PM +0300, Dmitry Baryshkov wrote:
> On 13/05/2022 15:42, Johan Hovold wrote:

> > If all qcom platform that can support more than 32 MSI require multiple
> > IRQs, how about adding num_vectors to the config instead and set
> > pp->has_split_msi_irq when cfg->num_vectors is set (or unconditionally
> > if you remove the corresponding warning you just added to the dwc host
> > code)?
> > 
> > At least some sc8280xp seem to only support 128 MSI (using 4 IRQs).
> 
> Nice idea, let's do this.

If at all possible it would be even better to just infer it from the
devicetree to avoid having to describe things in two places, though.

Johan