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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id 1-20020aca2801000000b00325cda1ff95sm5510341oix.20.2022.05.10.09.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 09:50:13 -0700 (PDT) Received: (nullmailer pid 2180170 invoked by uid 1000); Tue, 10 May 2022 16:50:12 -0000 Date: Tue, 10 May 2022 11:50:12 -0500 From: Rob Herring To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 0/8] dt-bindings: YAMLify pci/qcom,pcie schema Message-ID: References: <20220506152107.1527552-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220506152107.1527552-1-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, May 06, 2022 at 06:20:59PM +0300, Dmitry Baryshkov wrote: > Convert pci/qcom,pcie schema to YAML description. The first patch > introduces several warnings which are fixed by the other patches in the > series. > > Note regarding the snps,dw-pcie compatibility. The Qualcomm PCIe > controller uses Synopsys PCIe IP core. However it is not just fused to > the address space. Accessing PCIe registers requires several clocks and > regulators to be powered up. Thus it can be assumed that the qcom,pcie > bindings are not fully compatible with the snps,dw-pcie schema. > > Changes since v5: > - s/stance/stanza (pointed out by Bjorn Helgaas) > > Changes since v4: > - Change subjects to follow convention (suggested by Bjorn Helgaas) > > Changes since v3: > - Rebase on linux-next to include sm8150 patches > > Changes since v2 (still kudos to Krzyshtof): > - Readded reg-names conversion patch > - Mention wake-gpio update in the commit message > - Remove extra quotes in the schema > > Changes since v1 (all kudos to Krzyshtof): > - Dropped the reg-names patch. It will be handled separately > - Squashed the snps,dw-pcie removal (from schema) into the first patch > - Replaced deprecated perst-gpio and wake-gpio with perst-gpios and > wake-gpios in the examples and in DT files > - Moved common clocks/clock-names, resets/reset-names and power-domains > properties to the top level of the schema, leaving only platform > specifics in the conditional branches > - Dropped iommu-map/iommu-map-mask for now > - Added (missed) interrupt-cells, clocks, clock-names, resets, > reset-names properties to the required list (resets/reset-names are > removed in the next patch, as they are not used on msm8996) > - Fixed IRQ flags in the examples > - Merged apq8064/ipq8064 into the single condition statement > - Added extra empty lines > > Dmitry Baryshkov (8): > dt-bindings: PCI: qcom: Convert to YAML > dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms > dt-bindings: PCI: qcom: Specify reg-names explicitly > dt-bindings: PCI: qcom: Add schema for sc7280 chipset > arm64: dts: qcom: stop using snps,dw-pcie falback > arm: dts: qcom: stop using snps,dw-pcie falback > arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios > arm64: dts: qcom: replace deprecated perst-gpio with perst-gpios > > .../devicetree/bindings/pci/qcom,pcie.txt | 398 ---------- > .../devicetree/bindings/pci/qcom,pcie.yaml | 714 ++++++++++++++++++ What tree do these apply to because they don't apply to rc1. I'm assuming the PCI tree and Lorenzo should take them. Rob