From: Ira Weiny <ira.weiny@intel.com>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
"Alison Schofield" <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Dave Jiang <dave.jiang@intel.com>, <linux-kernel@vger.kernel.org>,
<linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH V10 6/9] cxl/port: Read CDAT table
Date: Thu, 9 Jun 2022 15:03:27 -0700 [thread overview]
Message-ID: <YqJuLwlmn0oLwHxj@iweiny-desk3> (raw)
In-Reply-To: <20220609092738.00007553@Huawei.com>
On Thu, Jun 09, 2022 at 09:27:38AM +0100, Jonathan Cameron wrote:
> On Wed, 8 Jun 2022 14:27:14 -0700
> Ira Weiny <ira.weiny@intel.com> wrote:
>
> > On Mon, Jun 06, 2022 at 11:15:41AM -0700, Ben Widawsky wrote:
> > > On 22-06-04 17:50:46, ira.weiny@intel.com wrote:
> > > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > >
> >
>
> [snip]
>
> > >
> > > > +
> > > > + entry = cdat_response_pl + 1;
> > > > + entry_dw = task.rv / sizeof(u32);
> > > > + /* Skip Header */
> > > > + entry_dw -= 1;
> > > > + entry_dw = min(length / 4, entry_dw);
> > > > + memcpy(data, entry, entry_dw * sizeof(u32));
> > > > + length -= entry_dw * sizeof(u32);
> > > > + data += entry_dw;
> > > > + entry_handle = FIELD_GET(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE, cdat_response_pl[0]);
> > >
> > > [0] looks suspicious...
> >
> > Actually I have to claim ignorance on this one. I've carried this from
> > Jonathan's original patches. I'm not as worried about the [0] as that is just
> > the first dword. But I'm confused as to this entry handle now.
> >
> > Jonathan? Help?
>
> Looks right to me. The entryhandle is a field in the upper 16 bits of the
> first dword defined in Read Entry Response table in the CXL spec and also
> used in the request of the next entry (which is more or less a CDAT structure)
> Two magic values.
> 0 - CDAT header (request only - can't be returned)
> 0xFFFF - No more entries.
Thanks!
>
> As we are reading the whole table, we write 0 to first request and from there
> on use the value returned in the response for the next request until we see
> 0xFFFF and stop.
>
> Note IIRC the meaning of entry handle was clarified in a CXL 2.0 errata as
> was a bit ambiguous in the original spec (we had two QEMU implementations
> briefly and they did different things :)
I see it now! I'm going to add a define for 0xFFFF as well.
Ira
>
> Jonathan
>
>
> >
> > >
> > > > +
> > > > + } while (entry_handle != 0xFFFF);
> > > > +
> > > > + return rc;
> > > > +}
> > > > +
>
>
next prev parent reply other threads:[~2022-06-09 22:03 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-05 0:50 [PATCH V10 0/9] CXL: Read CDAT and DSMAS data ira.weiny
2022-06-05 0:50 ` [PATCH V10 1/9] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-06-05 0:50 ` [PATCH V10 2/9] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-06-05 0:50 ` [PATCH V10 3/9] PCI: Create PCI library functions in support of DOE mailboxes ira.weiny
2022-06-20 8:39 ` Zhuo, Qiuxu
2022-06-20 21:46 ` Ira Weiny
2022-06-05 0:50 ` [PATCH V10 4/9] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-06-06 17:42 ` Ben Widawsky
2022-06-05 0:50 ` [PATCH V10 5/9] cxl/port: Find a DOE mailbox which supports CDAT ira.weiny
2022-06-06 17:48 ` Ben Widawsky
2022-06-08 19:39 ` Ira Weiny
2022-06-08 21:38 ` Ira Weiny
2022-06-05 0:50 ` [PATCH V10 6/9] cxl/port: Read CDAT table ira.weiny
2022-06-06 18:15 ` Ben Widawsky
2022-06-08 21:27 ` Ira Weiny
2022-06-09 8:27 ` Jonathan Cameron
2022-06-09 22:03 ` Ira Weiny [this message]
2022-06-05 0:50 ` [PATCH V10 7/9] cxl/port: Introduce cxl_cdat_valid() ira.weiny
2022-06-05 0:50 ` [PATCH V10 8/9] cxl/port: Retry reading CDAT on failure ira.weiny
2022-06-06 18:52 ` Ben Widawsky
2022-06-08 23:07 ` Ira Weiny
2022-06-05 0:50 ` [PATCH V10 9/9] cxl/port: Parse out DSMAS data from CDAT table ira.weiny
2022-06-06 19:32 ` Ben Widawsky
2022-06-09 0:34 ` Ira Weiny
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