From: Johan Hovold <johan@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@somainline.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: Re: [PATCH v5 2/5] phy: qcom-qmp-pcie: support separate tables for EP mode
Date: Tue, 27 Sep 2022 10:09:04 +0200 [thread overview]
Message-ID: <YzKvoN6hplGOKzsr@hovoldconsulting.com> (raw)
In-Reply-To: <20220926173435.881688-3-dmitry.baryshkov@linaro.org>
On Mon, Sep 26, 2022 at 08:34:32PM +0300, Dmitry Baryshkov wrote:
> The PCIe QMP PHY requires different programming sequences when being
> used for the RC (Root Complex) or for the EP (End Point) modes. Allow
> selecting the submode and thus selecting a set of PHY programming
> tables.
>
> Since the RC and EP modes share common some common init sequence, the
> common sequence is kept in the main table and the sequence differences
> are pushed to the extra tables.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 47 +++++++++++++++++++++---
> 1 file changed, 41 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index dc8f0f236212..dd7911879b10 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -14,6 +14,7 @@
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/of_address.h>
> +#include <linux/phy/pcie.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regulator/consumer.h>
> @@ -1320,10 +1321,14 @@ struct qmp_phy_cfg {
> /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
> const struct qmp_phy_cfg_tables tables;
> /*
> - * Additional init sequence for PHY blocks, providing additional
> - * register programming. Unless required it can be left omitted.
> + * Additional init sequences for PHY blocks, providing additional
> + * register programming. They are used for providing separate sequences
> + * for the Root Complex and for the End Point usecases.
"use cases", drop the second "for the".
> + *
> + * If EP mode is not supported, both tables can be left empty.
s/empty/unset/
> */
> const struct qmp_phy_cfg_tables *tables_rc;
> + const struct qmp_phy_cfg_tables *tables_ep;
>
> /* clock ids to be requested */
> const char * const *clk_list;
> +static int qmp_pcie_set_mode(struct phy *phy,
> + enum phy_mode mode, int submode)
No need for line break.
> +{
> + struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> + switch (submode) {
> + case PHY_MODE_PCIE_RC:
> + case PHY_MODE_PCIE_EP:
> + qphy->mode = submode;
> + break;
> + default:
> + dev_err(&phy->dev, "Unuspported submode %d\n", submode);
You forgot to fix the "unsupported" typo.
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
Looks good otherwise:
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Johan
next prev parent reply other threads:[~2022-09-27 8:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-26 17:34 [PATCH v5 0/5] PCI: qcom: Support using the same PHY for both RC and EP Dmitry Baryshkov
2022-09-26 17:34 ` [PATCH v5 1/5] phy: qcom-qmp-pcie: split register tables into common and extra parts Dmitry Baryshkov
2022-09-27 7:50 ` Johan Hovold
2022-09-26 17:34 ` [PATCH v5 2/5] phy: qcom-qmp-pcie: support separate tables for EP mode Dmitry Baryshkov
2022-09-27 8:09 ` Johan Hovold [this message]
2022-09-26 17:34 ` [PATCH v5 3/5] phy: qcom-qmp-pcie: Support SM8450 PCIe1 PHY in " Dmitry Baryshkov
2022-09-26 17:34 ` [PATCH v5 4/5] PCI: qcom: Setup PHY to work in RC mode Dmitry Baryshkov
2022-09-27 8:15 ` Johan Hovold
2022-09-26 17:34 ` [PATCH v5 5/5] PCI: qcom-ep: Setup PHY to work in EP mode Dmitry Baryshkov
2022-09-27 8:16 ` Johan Hovold
2022-09-27 9:20 ` Dmitry Baryshkov
2022-09-27 8:55 ` [PATCH v5 0/5] PCI: qcom: Support using the same PHY for both RC and EP Lorenzo Pieralisi
2022-09-27 9:15 ` Dmitry Baryshkov
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