From: Michal Hocko <mhocko@suse.com>
To: Adam Manzanares <a.manzanares@samsung.com>
Cc: "lsf-pc@lists.linux-foundation.org"
<lsf-pc@lists.linux-foundation.org>,
"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
"jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>,
"dave@stgolabs.net" <dave@stgolabs.net>,
Fan Ni <fan.ni@samsung.com>,
"dave.jiang@intel.com" <dave.jiang@intel.com>,
"ira.weiny@intel.com" <ira.weiny@intel.com>,
"alison.schofield@intel.com" <alison.schofield@intel.com>,
"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
"gourry.memverge@gmail.com" <gourry.memverge@gmail.com>,
"wj28.lee@gmail.com" <wj28.lee@gmail.com>,
"rientjes@google.com" <rientjes@google.com>,
"ruansy.fnst@fujitsu.com" <ruansy.fnst@fujitsu.com>,
"shradha.t@samsung.com" <shradha.t@samsung.com>,
"mcgrof@kernel.org" <mcgrof@kernel.org>,
Jim Harris <jim.harris@samsung.com>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
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Subject: Re: [LSF/MM/BPF TOPIC] CXL Development Discussions
Date: Tue, 7 May 2024 13:48:46 +0200 [thread overview]
Message-ID: <ZjoVHhiSLm3KRW63@tiehlicka> (raw)
In-Reply-To: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung>
On Mon 06-05-24 19:27:10, Adam Manzanares wrote:
> Hello all,
>
> I would like to have a discussion with the CXL development community about
> current outstanding issues and also invite developers interested in RAS and
> memory tiering to participate.
>
> The first topic I believe we should discuss is how we can ensure as a group
> that we are prioritizing upstream work. On a recent upstream CXL development
> discussion call there was a call to review more work. I apologize for not
> grabbing the link, but I believe Dave Jiang is leveraging patchwork and this
> link should be shared with others so we can help get more reviews where needed.
>
> The second topic I would like to discuss is how we integrate RAS features that
> have similar equivalents in the kernel. A CXL device can provide info about
> memory media errors in a similar fashion to memory controllers that have EDAC
> support. Discussions have been put on the list and I would like to hear thoughts
> from the community about where this should go [1]. On the same topic CXL has
> port level RAS features and the PCIe DW series touched on this issue [2]
>
> The third topic I would like to discuss is how we can get a set of common
> benchmarks for memory tiering evaluations. Our team has done some initial
> work in this space, but we want to hear more from end users about their
> workloads of concern. There was a proposal related to this topic, but from what
> I understand no meeting has been held [3].
>
> The last topic that I believe is worth discussion is how do we come up with
> a baseline for testing. I am aware of 3 efforts that could be used cxl_test,
> qemu, and uunit testing framework [4].
This seems to be quite a lot for a single time slot. I think it would
make sense to split that into more slots. WDYT?
--
Michal Hocko
SUSE Labs
next prev parent reply other threads:[~2024-05-07 11:48 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20240506192712uscas1p225316f79bb69f979b647d2a06a00a25f@uscas1p2.samsung.com>
2024-05-06 19:27 ` [LSF/MM/BPF TOPIC] CXL Development Discussions Adam Manzanares
2024-05-06 20:28 ` Dave Jiang
2024-05-06 22:58 ` Dan Williams
2024-05-08 18:08 ` Adam Manzanares
2024-05-06 23:47 ` Dan Williams
2024-05-07 18:50 ` Luis Chamberlain
2024-05-08 18:38 ` Adam Manzanares
2024-05-08 19:30 ` Luis Chamberlain
2024-05-09 18:14 ` Song Liu
2024-05-09 4:19 ` Dan Williams
2024-05-08 18:26 ` Adam Manzanares
2024-05-07 11:48 ` Michal Hocko [this message]
2024-05-08 18:35 ` Adam Manzanares
2024-05-12 13:07 ` Michal Hocko
2024-05-13 12:12 ` Davidlohr Bueso
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