From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@broadcom.com>,
Jeremy Linton <jeremy.linton@arm.com>,
Andrew Murray <amurray@thegoodpenguin.co.uk>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-rpi-kernel@lists.infradead.org>,
"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
<linux-pci@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/4] PCI: brcmstb: Fix window register offset from 4 to 8
Date: Tue, 05 May 2020 15:25:07 +0200 [thread overview]
Message-ID: <a23de9954ffca762bdcd075c4ed02b1a17af3eb5.camel@suse.de> (raw)
In-Reply-To: <20200501142831.35174-3-james.quinlan@broadcom.com>
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On Fri, 2020-05-01 at 10:28 -0400, Jim Quinlan wrote:
> From: Jim Quinlan <jquinlan@broadcom.com>
>
> The outbound memory window registers were being referenced
> with an incorrect stride offset. This probably wasn't noticed
> previously as there was likely only one such window employed.
>
> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
>
> Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller
> driver")
> ---
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Regards,
Nicolas
> drivers/pci/controller/pcie-brcmstb.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c
> b/drivers/pci/controller/pcie-brcmstb.c
> index 454917ee9241..5b0dec5971b8 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -54,11 +54,11 @@
>
> #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> #define PCIE_MEM_WIN0_LO(win) \
> - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
>
> #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> #define PCIE_MEM_WIN0_HI(win) \
> - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
>
> #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
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next prev parent reply other threads:[~2020-05-05 13:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-01 14:28 [PATCH v2 0/4] PCI: brcmstb: Some minor fixes/features Jim Quinlan
2020-05-01 14:28 ` [PATCH v2 1/4] PCI: brcmstb: Don't clk_put() a managed clock Jim Quinlan
2020-05-05 13:23 ` Nicolas Saenz Julienne
2020-05-01 14:28 ` [PATCH v2 2/4] PCI: brcmstb: Fix window register offset from 4 to 8 Jim Quinlan
2020-05-05 13:25 ` Nicolas Saenz Julienne [this message]
2020-05-01 14:28 ` [PATCH v2 3/4] dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s' Jim Quinlan
2020-05-01 15:48 ` Rob Herring
2020-05-01 14:28 ` [PATCH v2 4/4] PCI: brcmstb: Disable L0s component of ASPM if requested Jim Quinlan
2020-05-05 13:31 ` Nicolas Saenz Julienne
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