From: Vignesh Raghavendra <vigneshr@ti.com>
To: Siddharth Vadapalli <s-vadapalli@ti.com>, <tjoseph@cadence.com>,
<lpieralisi@kernel.org>, <robh@kernel.org>, <kw@linux.com>,
<bhelgaas@google.com>, <nadeem@cadence.com>
Cc: <linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <srk@ti.com>, <nm@ti.com>
Subject: Re: [RESEND PATCH] PCI: cadence: Fix Gen2 Link Retraining process
Date: Wed, 25 Jan 2023 19:45:46 +0530 [thread overview]
Message-ID: <a9e3fc94-cf0d-2cfd-640f-c81dfe35f05a@ti.com> (raw)
In-Reply-To: <20230102075656.260333-1-s-vadapalli@ti.com>
On 02/01/23 1:26 pm, Siddharth Vadapalli wrote:
> The Link Retraining process is initiated to account for the Gen2 defect in
> the Cadence PCIe controller in J721E SoC. The errata corresponding to this
> is i2085, documented at:
> https://www.ti.com/lit/er/sprz455c/sprz455c.pdf
>
> The existing workaround implemented for the errata waits for the Data Link
> initialization to complete and assumes that the link retraining process
> at the Physical Layer has completed. However, it is possible that the
> Physical Layer training might be ongoing as indicated by the
> PCI_EXP_LNKSTA_LT bit in the PCI_EXP_LNKSTA register.
>
> Fix the existing workaround, to ensure that the Physical Layer training
> has also completed, in addition to the Data Link initialization.
>
> Fixes: 4740b969aaf5 ("PCI: cadence: Retrain Link to work around Gen2 training defect")
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> .../controller/cadence/pcie-cadence-host.c | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 940c7dd701d6..5b14f7ee3c79 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -12,6 +12,8 @@
>
> #include "pcie-cadence.h"
>
> +#define LINK_RETRAIN_TIMEOUT HZ
> +
> static u64 bar_max_size[] = {
> [RP_BAR0] = _ULL(128 * SZ_2G),
> [RP_BAR1] = SZ_2G,
> @@ -77,6 +79,27 @@ static struct pci_ops cdns_pcie_host_ops = {
> .write = pci_generic_config_write,
> };
>
> +static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie)
> +{
> + u32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
> + unsigned long end_jiffies;
> + u16 lnk_stat;
> +
> + /* Wait for link training to complete. Exit after timeout. */
> + end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
> + do {
> + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
> + if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
> + break;
> + usleep_range(0, 1000);
> + } while (time_before(jiffies, end_jiffies));
> +
> + if (!(lnk_stat & PCI_EXP_LNKSTA_LT))
> + return 0;
> +
> + return -ETIMEDOUT;
> +}
> +
> static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
> {
> struct device *dev = pcie->dev;
> @@ -118,6 +141,10 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
> cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
> lnk_ctl);
>
> + ret = cdns_pcie_host_training_complete(pcie);
> + if (ret)
> + return ret;
> +
> ret = cdns_pcie_host_wait_for_link(pcie);
> }
> return ret;
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Regards
Vignesh
prev parent reply other threads:[~2023-01-25 14:16 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-02 7:56 [RESEND PATCH] PCI: cadence: Fix Gen2 Link Retraining process Siddharth Vadapalli
2023-01-10 10:33 ` Siddharth Vadapalli
2023-01-25 14:15 ` Vignesh Raghavendra [this message]
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