From: Yicong Yang <yangyicong@huawei.com>
To: John Garry <john.garry@huawei.com>,
Yicong Yang <yangyicong@hisilicon.com>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"helgaas@kernel.org" <helgaas@kernel.org>,
"alexander.shishkin@linux.intel.com"
<alexander.shishkin@linux.intel.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"will@kernel.org" <will@kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"mathieu.poirier@linaro.org" <mathieu.poirier@linaro.org>,
"suzuki.poulose@arm.com" <suzuki.poulose@arm.com>,
"mike.leach@linaro.org" <mike.leach@linaro.org>,
"leo.yan@linaro.org" <leo.yan@linaro.org>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
"daniel.thompson@linaro.org" <daniel.thompson@linaro.org>,
"joro@8bytes.org" <joro@8bytes.org>,
Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
"robin.murphy@arm.com" <robin.murphy@arm.com>,
"peterz@infradead.org" <peterz@infradead.org>,
"mingo@redhat.com" <mingo@redhat.com>,
"acme@kernel.org" <acme@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"coresight@lists.linaro.org" <coresight@lists.linaro.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-perf-users@vger.kernel.org"
<linux-perf-users@vger.kernel.org>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>
Cc: "Zengtao (B)" <prime.zeng@hisilicon.com>,
"liuqi (BA)" <liuqi115@huawei.com>,
Zhangshaokun <zhangshaokun@hisilicon.com>,
Linuxarm <linuxarm@huawei.com>,
"Song Bao Hua (Barry Song)" <song.bao.hua@hisilicon.com>
Subject: Re: [PATCH v3 8/8] iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity
Date: Tue, 8 Feb 2022 19:21:05 +0800 [thread overview]
Message-ID: <ae45a637-2c67-4126-3007-6829320d5659@huawei.com> (raw)
In-Reply-To: <4f6f6e0f-4398-3018-cc35-6aa7ea1305fe@huawei.com>
On 2022/2/8 16:05, John Garry wrote:
> On 24/01/2022 13:11, Yicong Yang wrote:
>> The DMA of HiSilicon PTT device can only work with identical
>> mapping. So add a quirk for the device to force the domain
>> passthrough.
>
> This patch should be earlier in the series, before the PTT driver, and the comment on hisi_ptt_check_iommu_mapping() should mention what is going on here.
>
ok I'll reorder the serives and modify the comments of hisi_ptt_check_iommu_mapping() like:
/*
* The DMA of PTT trace can only use direct mapping, due to some
* hardware restriction. Check whether there is an iommu or the
* policy of the iommu domain is passthrough, otherwise the trace
* cannot work.
*
* The PTT device is supposed to behind the arm smmu v3, which
* should have passthrough the device by a quirk. Otherwise user
* should manually set the iommu domain type to identity through
* sysfs.
*/
>>
>> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
>> ---
>> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> index 6dc6d8b6b368..6f67a2b1dd27 100644
>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
>> @@ -2838,6 +2838,21 @@ static int arm_smmu_dev_disable_feature(struct device *dev,
>> }
>> }
>> +#define IS_HISI_PTT_DEVICE(pdev) ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI && \
>> + (pdev)->device == 0xa12e)
>
> I assume that not all revisions will require this check, right?
>
For current revisions it's necessary.
>> +
>> +static int arm_smmu_def_domain_type(struct device *dev)
>> +{
>> + if (dev_is_pci(dev)) {
>> + struct pci_dev *pdev = to_pci_dev(dev);
>> +
>> + if (IS_HISI_PTT_DEVICE(pdev))
>> + return IOMMU_DOMAIN_IDENTITY;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> static struct iommu_ops arm_smmu_ops = {
>> .capable = arm_smmu_capable,
>> .domain_alloc = arm_smmu_domain_alloc,
>> @@ -2863,6 +2878,7 @@ static struct iommu_ops arm_smmu_ops = {
>> .sva_unbind = arm_smmu_sva_unbind,
>> .sva_get_pasid = arm_smmu_sva_get_pasid,
>> .page_response = arm_smmu_page_response,
>> + .def_domain_type = arm_smmu_def_domain_type,
>> .pgsize_bitmap = -1UL, /* Restricted during device attach */
>> .owner = THIS_MODULE,
>> };
>
> .
next prev parent reply other threads:[~2022-02-08 11:31 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 13:11 [PATCH v3 0/8] Add support for HiSilicon PCIe Tune and Trace device Yicong Yang
2022-01-24 13:11 ` [PATCH v3 1/8] hwtracing: Add trace function " Yicong Yang
2022-02-07 11:42 ` Jonathan Cameron
2022-02-08 11:07 ` Yicong Yang
2022-02-14 12:51 ` Yicong Yang
2022-02-07 18:11 ` John Garry
2022-02-08 8:57 ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 2/8] hisi_ptt: Register PMU device for PTT trace Yicong Yang
2022-02-07 11:42 ` Jonathan Cameron
2022-02-08 7:41 ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 3/8] hisi_ptt: Add support for dynamically updating the filter list Yicong Yang
2022-01-24 13:11 ` [PATCH v3 4/8] hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device Yicong Yang
2022-02-07 11:49 ` Jonathan Cameron
2022-02-08 7:08 ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 5/8] perf tool: Add support for HiSilicon PCIe Tune and Trace device driver Yicong Yang
2022-02-07 11:55 ` Jonathan Cameron
2022-01-24 13:11 ` [PATCH v3 6/8] docs: Add HiSilicon PTT device driver documentation Yicong Yang
2022-02-07 12:12 ` Jonathan Cameron
2022-02-08 11:09 ` Yicong Yang
2022-01-24 13:11 ` [PATCH v3 7/8] MAINTAINERS: Add maintainer for HiSilicon PTT driver Yicong Yang
2022-01-24 13:11 ` [PATCH v3 8/8] iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity Yicong Yang
2022-02-08 8:05 ` John Garry
2022-02-08 11:21 ` Yicong Yang [this message]
2022-02-08 11:56 ` John Garry
2022-02-08 12:20 ` Yicong Yang
2022-02-14 12:55 ` Yicong Yang
2022-02-15 13:00 ` Will Deacon
2022-02-15 13:30 ` Robin Murphy
2022-02-15 13:42 ` Will Deacon
2022-02-15 14:29 ` Robin Murphy
2022-02-16 9:35 ` Yicong Yang
2022-02-07 9:40 ` [PATCH v3 0/8] Add support for HiSilicon PCIe Tune and Trace device Yicong Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ae45a637-2c67-4126-3007-6829320d5659@huawei.com \
--to=yangyicong@huawei.com \
--cc=acme@kernel.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=coresight@lists.linaro.org \
--cc=daniel.thompson@linaro.org \
--cc=gregkh@linuxfoundation.org \
--cc=helgaas@kernel.org \
--cc=iommu@lists.linux-foundation.org \
--cc=john.garry@huawei.com \
--cc=jonathan.cameron@huawei.com \
--cc=joro@8bytes.org \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linuxarm@huawei.com \
--cc=liuqi115@huawei.com \
--cc=lorenzo.pieralisi@arm.com \
--cc=mark.rutland@arm.com \
--cc=mathieu.poirier@linaro.org \
--cc=mike.leach@linaro.org \
--cc=mingo@redhat.com \
--cc=peterz@infradead.org \
--cc=prime.zeng@hisilicon.com \
--cc=robin.murphy@arm.com \
--cc=shameerali.kolothum.thodi@huawei.com \
--cc=song.bao.hua@hisilicon.com \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
--cc=yangyicong@hisilicon.com \
--cc=zhangshaokun@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).