From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CA81C43141 for ; Thu, 14 Nov 2019 03:52:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C0A3206EC for ; Thu, 14 Nov 2019 03:52:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726957AbfKNDww (ORCPT ); Wed, 13 Nov 2019 22:52:52 -0500 Received: from mga11.intel.com ([192.55.52.93]:8089 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726557AbfKNDww (ORCPT ); Wed, 13 Nov 2019 22:52:52 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Nov 2019 19:52:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,302,1569308400"; d="scan'208";a="404840603" Received: from linux.intel.com ([10.54.29.200]) by fmsmga005.fm.intel.com with ESMTP; 13 Nov 2019 19:52:51 -0800 Received: from [10.226.39.46] (unknown [10.226.39.46]) by linux.intel.com (Postfix) with ESMTP id 734FE58049A; Wed, 13 Nov 2019 19:52:48 -0800 (PST) Subject: Re: [PATCH v6 2/3] dwc: PCI: intel: PCIe RC controller driver To: Andy Shevchenko Cc: gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, andrew.murray@arm.com, helgaas@kernel.org, jingoohan1@gmail.com, robh@kernel.org, martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com References: <897ef494f39291797a92efb87a59961d36384019.1573613534.git.eswara.kota@linux.intel.com> <20191113110009.GC32742@smile.fi.intel.com> From: Dilip Kota Message-ID: Date: Thu, 14 Nov 2019 11:52:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191113110009.GC32742@smile.fi.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 11/13/2019 7:00 PM, Andy Shevchenko wrote: > On Wed, Nov 13, 2019 at 03:21:21PM +0800, Dilip Kota wrote: >> Add support to PCIe RC controller on Intel Gateway SoCs. >> PCIe controller is based of Synopsys DesignWare PCIe core. >> >> Intel PCIe driver requires Upconfigure support, Fast Training >> Sequence and link speed configurations. So adding the respective >> helper functions in the PCIe DesignWare framework. >> It also programs hardware autonomous speed during speed >> configuration so defining it in pci_regs.h. >> +#include >> +#include > I hardly see the use of above... Thanks for pointing it. Yes, it can be removed. I have again cross checked all the header files , i see below files can also be removed. #include #include #include >> + if (device_property_read_u32(dev, "reset-assert-ms", &lpp->rst_intrvl)) >> + lpp->rst_intrvl = RESET_INTERVAL_MS; > ...perhaps you need to add > > #include > > instead. I see this header file is  already getting included in the driver through linux/phy/phy.h => linux/of.h (of.h has #include ) Thanks for reviewing the patch, i will update the driver and submit the next patch version. Regards, Dilip >