From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: "Abel Vesa" <abel.vesa@linaro.org>,
"Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@linaro.org>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Manivannan Sadhasivam" <mani@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 2/2] PCI: qcom: Add SM8550 PCIe support
Date: Fri, 20 Jan 2023 09:38:19 +0100 [thread overview]
Message-ID: <ba338259-e5b4-2a15-9305-b74c04f23d48@linaro.org> (raw)
In-Reply-To: <20230119112453.3393911-2-abel.vesa@linaro.org>
On 19/01/2023 12:24, Abel Vesa wrote:
> Add compatible for both PCIe found on SM8550.
> Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>
> The v2 was here:
> https://lore.kernel.org/all/20230118111704.3553542-2-abel.vesa@linaro.org/
>
> Changes since v2:
> * none
>
> Changes since v1:
> * changed the subject line prefix for the patch to match the history,
> like Bjorn Helgaas suggested.
> * added Konrad's R-b tag
>
>
> drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 77e5dc7b88ad..85988b3fd4f6 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 {
>
> /* 6 clocks typically, 7 for sm8250 */
> struct qcom_pcie_resources_2_7_0 {
> - struct clk_bulk_data clks[12];
> + struct clk_bulk_data clks[13];
> int num_clks;
> struct regulator_bulk_data supplies[2];
> struct reset_control *pci_reset;
> @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> res->clks[idx++].id = "noc_aggr_4";
> res->clks[idx++].id = "noc_aggr_south_sf";
> res->clks[idx++].id = "cnoc_qx";
> + res->clks[idx++].id = "cnoc_pcie_sf_axi";
>
> num_opt_clks = idx - num_clks;
> res->num_clks = idx;
> @@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
> { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
> { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
> + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
This does not match your bindings. Basically, this is very similar to
other models but bindings suggest otherwise - several new properties,
optional existing properties.
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-01-20 8:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-19 11:24 [PATCH v3 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible Abel Vesa
2023-01-19 11:24 ` [PATCH v3 2/2] PCI: qcom: Add SM8550 PCIe support Abel Vesa
2023-01-20 8:38 ` Krzysztof Kozlowski [this message]
2023-01-20 8:37 ` [PATCH v3 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible Krzysztof Kozlowski
2023-01-23 16:40 ` Abel Vesa
2023-01-23 17:20 ` Krzysztof Kozlowski
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