* [PATCH] PCI: Change message to debug level in pci_set_cacheline_size
@ 2020-12-08 17:57 Heiner Kallweit
2020-12-08 22:39 ` Bjorn Helgaas
0 siblings, 1 reply; 2+ messages in thread
From: Heiner Kallweit @ 2020-12-08 17:57 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: linux-pci
Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an
annnoying message like the following that results in user questions
whether something is broken.
xhci_hcd 0000:00:15.0: cache line size of 64 is not supported
Root cause of the message is that on several (most?) chips the
cache line size register is hard-wired to 0.
Change this message to debug level, an interested caller can still
inform the user (if deemed helpful) based on the return code.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
drivers/pci/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b7f0883d6..9a5500287 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4324,7 +4324,7 @@ int pci_set_cacheline_size(struct pci_dev *dev)
if (cacheline_size == pci_cache_line_size)
return 0;
- pci_info(dev, "cache line size of %d is not supported\n",
+ pci_dbg(dev, "cache line size of %d is not supported\n",
pci_cache_line_size << 2);
return -EINVAL;
--
2.29.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] PCI: Change message to debug level in pci_set_cacheline_size
2020-12-08 17:57 [PATCH] PCI: Change message to debug level in pci_set_cacheline_size Heiner Kallweit
@ 2020-12-08 22:39 ` Bjorn Helgaas
0 siblings, 0 replies; 2+ messages in thread
From: Bjorn Helgaas @ 2020-12-08 22:39 UTC (permalink / raw)
To: Heiner Kallweit; +Cc: Bjorn Helgaas, linux-pci
On Tue, Dec 08, 2020 at 06:57:02PM +0100, Heiner Kallweit wrote:
> Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an
> annnoying message like the following that results in user questions
> whether something is broken.
> xhci_hcd 0000:00:15.0: cache line size of 64 is not supported
>
> Root cause of the message is that on several (most?) chips the
> cache line size register is hard-wired to 0.
Interesting. Per spec, for PCIe, I think the Cache Line Size is
supposed to be read/write except on virtual functions, where it is RO
Zero (and the example above doesn't look like a VF). It doesn't *do*
anything for most PCIe devices, but it's still supposed to be
writable.
But it's not completely clear for conventional PCI -- PCI r3.0, sec
6.2.4, says the register "must be implemented by master devices that
can generate the Memory Write and Invalidate command." So I guess if
a device doesn't support MWI, maybe it doesn't have to be writable.
Applied to pci/misc for v5.11, thanks!
> Change this message to debug level, an interested caller can still
> inform the user (if deemed helpful) based on the return code.
>
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
> ---
> drivers/pci/pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index b7f0883d6..9a5500287 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -4324,7 +4324,7 @@ int pci_set_cacheline_size(struct pci_dev *dev)
> if (cacheline_size == pci_cache_line_size)
> return 0;
>
> - pci_info(dev, "cache line size of %d is not supported\n",
> + pci_dbg(dev, "cache line size of %d is not supported\n",
> pci_cache_line_size << 2);
>
> return -EINVAL;
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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