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From: Chris Friesen <>
To: Keith Busch <>
Cc: Thomas Gleixner <>,
	Bjorn Helgaas <>,, Christoph Hellwig <>,
	Nitesh Narayan Lal <>
Subject: Re: PCI, isolcpus, and irq affinity
Date: Thu, 15 Oct 2020 12:47:23 -0600	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

On 10/12/2020 1:07 PM, Keith Busch wrote:
> On Mon, Oct 12, 2020 at 12:58:41PM -0600, Chris Friesen wrote:
>> On 10/12/2020 11:50 AM, Thomas Gleixner wrote:
>>> On Mon, Oct 12 2020 at 11:58, Bjorn Helgaas wrote:
>>>> On Mon, Oct 12, 2020 at 09:49:37AM -0600, Chris Friesen wrote:
>>>>> I've got a linux system running the RT kernel with threaded irqs.  On
>>>>> startup we affine the various irq threads to the housekeeping CPUs, but I
>>>>> recently hit a scenario where after some days of uptime we ended up with a
>>>>> number of NVME irq threads affined to application cores instead (not good
>>>>> when we're trying to run low-latency applications).
>>> These threads and the associated interupt vectors are completely
>>> harmless and fully idle as long as there is nothing on those isolated
>>> CPUs which does disk I/O.
>> Some of the irq threads are affined (by the kernel presumably) to multiple
>> CPUs (nvme1q2 and nvme0q2 were both affined 0x38000038, a couple of other
>> queues were affined 0x1c00001c0).
> That means you have more CPUs than your controller has queues. When that
> happens, some sharing of the queue resources among CPUs is required.

Is it required that every CPU is part of the mask for at least one queue?

If we can preferentially route interrupts to the housekeeping CPUs (for 
queues with multiple CPUs in the mask), how is that different than just 
affining all the queues to the housekeeping CPUs and leaving the 
isolated CPUs out of the mask entirely?


  parent reply	other threads:[~2020-10-15 18:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-12 15:49 Chris Friesen
2020-10-12 16:58 ` Bjorn Helgaas
2020-10-12 17:39   ` Sean V Kelley
2020-10-12 19:18     ` Chris Friesen
2020-10-12 17:42   ` Nitesh Narayan Lal
2020-10-12 17:50   ` Thomas Gleixner
2020-10-12 18:58     ` Chris Friesen
2020-10-12 19:07       ` Keith Busch
2020-10-12 19:44         ` Thomas Gleixner
2020-10-15 18:47         ` Chris Friesen [this message]
2020-10-15 19:02           ` Keith Busch
2020-10-12 19:31       ` Thomas Gleixner
2020-10-12 20:24         ` David Woodhouse
2020-10-12 22:25           ` Thomas Gleixner

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