From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4C26C43387 for ; Wed, 16 Jan 2019 10:33:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6A8B7206C2 for ; Wed, 16 Jan 2019 10:33:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=synopsys.com header.i=@synopsys.com header.b="DHsrkH7d" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731941AbfAPKdk (ORCPT ); Wed, 16 Jan 2019 05:33:40 -0500 Received: from smtprelay4.synopsys.com ([198.182.47.9]:45828 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731965AbfAPKdk (ORCPT ); Wed, 16 Jan 2019 05:33:40 -0500 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 02AB824E0600; Wed, 16 Jan 2019 02:33:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=synopsys.com; s=mail; t=1547634820; bh=pfl0E3F7BNxZvxvmFVSIpoTPwRnnbaXw6/O4v6IcIHQ=; h=Subject:To:CC:References:From:Date:In-Reply-To:From; b=DHsrkH7dJPwUjLpPSE97AMQvFBmLah/fvErScXhCyJhtRM+YzmILxIgUsrFL+wPzz YfNliO7KdZYnXZgA8mSMbPeHBgHO9HFk+PWG0JM/5v02MkK/CDFxS3t/QoU5Uz9otw EZNA80ncDf2nYwFOoDDG4MVjkWXMcm09Ac36ENSWMaLb2kgAFh3wPRS7WHFoCCLOUT qeGpKR/qT1YGw6t2VGiHOcka8ZPySZ8Lxw4B51SfsB8rFX/V/ruEb+QvLxMibbTAVi eUKPdxyYBCFnsaPrjDE/yg/E1/r5XULe+47zumuPS/bmRnn1z/ACb0d9erRIdNw39V uDuCVw8xstj1g== Received: from US01WXQAHTC1.internal.synopsys.com (us01wxqahtc1.internal.synopsys.com [10.12.238.230]) by mailhost.synopsys.com (Postfix) with ESMTP id DFEE24694; Wed, 16 Jan 2019 02:33:39 -0800 (PST) Received: from DE02WEHTCB.internal.synopsys.com (10.225.19.94) by US01WXQAHTC1.internal.synopsys.com (10.12.238.230) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 16 Jan 2019 02:33:39 -0800 Received: from DE02WEHTCA.internal.synopsys.com (10.225.19.92) by DE02WEHTCB.internal.synopsys.com (10.225.19.94) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 16 Jan 2019 11:33:37 +0100 Received: from [10.107.19.24] (10.107.19.24) by DE02WEHTCA.internal.synopsys.com (10.225.19.80) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 16 Jan 2019 11:33:37 +0100 Subject: Re: [RFC v3 2/7] dmaengine: Add Synopsys eDMA IP version 0 support To: Gustavo Pimentel , , CC: Vinod Koul , Dan Williams , Eugeniy Paltsev , Andy Shevchenko , Russell King , Niklas Cassel , Joao Pinto , Jose Abreu , Luis Oliveira , Vitor Soares , Nelson Costa , "Pedro Sousa" References: From: Jose Abreu Message-ID: Date: Wed, 16 Jan 2019 10:33:35 +0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.107.19.24] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi Gustavo, On 1/11/2019 6:33 PM, Gustavo Pimentel wrote: > Add support for the eDMA IP version 0 driver for both register maps (legacy > and unroll). > > The legacy register mapping was the initial implementation, which consisted > in having all registers belonging to channels multiplexed, which could be > change anytime (which could led a race-condition) by view port register > (access to only one channel available each time). > > This register mapping is not very effective and efficient in a multithread > environment, which has led to the development of unroll registers mapping, > which consists of having all channels registers accessible any time by > spreading all channels registers by an offset between them. > > This version supports a maximum of 16 independent channels (8 write + > 8 read), which can run simultaneously. > > Implements a scatter-gather transfer through a linked list, where the size > of linked list depends on the allocated memory divided equally among all > channels. > > Each linked list descriptor can transfer from 1 byte to 4 Gbytes and is > alignmented to DWORD. > > Both SAR (Source Address Register) and DAR (Destination Address Register) > are alignmented to byte. > > Changes: > RFC v1->RFC v2: > - Replace comments // (C99 style) by /**/ > - Replace magic numbers by defines > - Replace boolean return from ternary operation by a double negation > operation > - Replace QWORD_HI/QWORD_LO macros by upper_32_bits()/lower_32_bits() > - Fix the headers of the .c and .h files according to the most recent > convention > - Fix errors and checks pointed out by checkpatch with --strict option > - Replace patch small description tag from dma by dmaengine > - Refactor code to replace atomic_t by u32 variable type > RFC v2->RFC v3: > - Code rewrite to use FIELD_PREP() and FIELD_GET() > - Add define to magic numbers > - Fix minor bugs > > Signed-off-by: Gustavo Pimentel > Cc: Vinod Koul > Cc: Dan Williams > Cc: Eugeniy Paltsev > Cc: Andy Shevchenko > Cc: Russell King > Cc: Niklas Cassel > Cc: Joao Pinto > Cc: Jose Abreu > Cc: Luis Oliveira > Cc: Vitor Soares > Cc: Nelson Costa > Cc: Pedro Sousa > +void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) > +{ > + struct dw_edma_chan *chan = chunk->chan; > + struct dw_edma *dw = chan->chip->dw; > + u32 tmp; > + u64 llp; > + > + dw_edma_v0_core_write_chunk(chunk); > + > + if (first) { > + /* Enable engine */ > + SET_RW(dw, chan->dir, engine_en, BIT(0)); > + /* Interrupt unmask - done, abort */ > + tmp = GET_RW(dw, chan->dir, int_mask); > + tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); > + tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); > + SET_RW(dw, chan->dir, int_mask, tmp); > + /* Linked list error */ > + tmp = GET_RW(dw, chan->dir, linked_list_err_en); > + tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id)); > + SET_RW(dw, chan->dir, linked_list_err_en, tmp); > + /* Channel control */ > + SET_CH(dw, chan->dir, chan->id, ch_control1, > + (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); > + /* Linked list - low, high */ > + llp = cpu_to_le64(chunk->ll_region.paddr); > + SET_CH(dw, chan->dir, chan->id, llp_low, lower_32_bits(llp)); > + SET_CH(dw, chan->dir, chan->id, llp_high, upper_32_bits(llp)); > + } > + /* Doorbell */ Not sure if DMA subsystem does this but maybe you need some kind of barrier to ensure everything is coherent before granting control to eDMA ? > + SET_RW(dw, chan->dir, doorbell, > + FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); > +} > +