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From: Lucas Stach <l.stach@pengutronix.de>
To: Richard Zhu <hongxing.zhu@nxp.com>,
	andrew.smirnov@gmail.com, shawnguo@kernel.org, kw@linux.com,
	bhelgaas@google.com, stefan@agner.ch, lorenzo.pieralisi@arm.com
Cc: linux-pci@vger.kernel.org, linux-imx@nxp.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de
Subject: Re: [PATCH v2 1/3] dt-bindings: imx6q-pcie: add one regulator used to power up pcie phy
Date: Wed, 24 Mar 2021 10:26:52 +0100	[thread overview]
Message-ID: <ca22113963e9499ec47839c627840d7ffee157b3.camel@pengutronix.de> (raw)
In-Reply-To: <1616564059-8713-2-git-send-email-hongxing.zhu@nxp.com>

Hi Richard,

Am Mittwoch, dem 24.03.2021 um 13:34 +0800 schrieb Richard Zhu:
> Both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe PHY.
> In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
> sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design,
> the VREG_BYPASS bits of GPR registers should be cleared from default
> value 1b'1 to 1b'0. Thus, the internal 3v3 to 1v8 translator would be
> turned on.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index de4b2baf91e8..3248b7192ced 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -38,6 +38,12 @@ Optional properties:
>    The regulator will be enabled when initializing the PCIe host and
>    disabled either as part of the init process or when shutting down the
>    host.
> +- vph-supply: Should specify the regulator in charge of PCIe PHY power.
> +  On i.MX8MQ, both 1.8v and 3.3v power supplies can be used by i.MX8MQ PCIe
> +  PHY. In default, the PCIE_VPH voltage is suggested to be 1.8v refer to data
> +  sheet. When PCIE_VPH is supplied by 3.3v in the HW schematic design, the
> +  VREG_BYPASS bits of GPR registers should be cleared from default value 1b'1
> +  to 1b'0.

This description of the internal driver behavior does not belong into a
DT binding description.
Instead the binding should describe the function of the regulator
exactly. From the datasheet I can see that there are actually 3
supplies (VPH, VP, VPTX) going into the PCIe PHY, so "regulator in
charge of PCIe PHY power" doesn't seem like a very accurate
description.

Regards,
Lucas


  reply	other threads:[~2021-03-24  9:27 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-24  5:34 [PATCH v2 0/3] " Richard Zhu
2021-03-24  5:34 ` [PATCH v2 1/3] dt-bindings: imx6q-pcie: " Richard Zhu
2021-03-24  9:26   ` Lucas Stach [this message]
2021-03-24  5:34 ` [PATCH v2 2/3] arm64: dts: imx8mq-evk: " Richard Zhu
2021-03-24  5:34 ` [PATCH v2 3/3] PCI: imx: clear vreg bypass when pcie vph voltage is 3v3 Richard Zhu
2021-03-24  9:30   ` Lucas Stach
2021-03-25  2:22     ` [EXT] " Richard Zhu

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