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From: "Stefan Bühler" <stefan.buehler@tik.uni-stuttgart.de>
To: Thomas Gleixner <tglx@linutronix.de>, sean.v.kelley@linux.intel.com
Cc: bhelgaas@google.com, bp@alien8.de, corbet@lwn.net,
	kar.hin.ong@ni.com, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	mingo@redhat.com, sassmann@kpanic.de, x86@kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Subject: Re: boot interrupt quirk (also in 4.19.y) breaks serial ports (was: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets)
Date: Wed, 25 Nov 2020 14:41:19 +0100	[thread overview]
Message-ID: <d512469f-de04-2f66-ca42-21ec3c5331ba@tik.uni-stuttgart.de> (raw)
In-Reply-To: <87zh35k5xa.fsf@nanos.tec.linutronix.de>

[-- Attachment #1: Type: text/plain, Size: 1128 bytes --]

Hi tglx,

On 11/25/20 12:54 PM, Thomas Gleixner wrote:
> Stefan,
> 
> On Wed, Sep 16 2020 at 12:12, Stefan Bühler wrote:
> 
> sorry for the delay. This fell through the cracks.
> 
>> this quirk breaks our serial ports PCIe card (i.e. we don't see any 
>> output from the connected devices; no idea whether anything we send 
>> reaches them):
>>
>> 05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa)
>> 06:00.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart)
>> 06:00.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled)
>> 06:01.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart)
>> 06:01.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART)
>> function 0 (Disabled)
> 
> Can you please provide the output of:
> 
>  for ID in 05:00.0 06:00.0 06:00.1 06:01.0 06:01.1; do lspci -s $ID -vvv; done
> 

See attachment.

Also I boot the affected systems now with "pci=noioapicquirk", which
"solves" the issue too (instead of patching the kernel).

cheers,
Stefan

[-- Attachment #2: oxford-serial-lspci.txt --]
[-- Type: text/plain, Size: 3721 bytes --]

05:00.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa) (prog-if 00 [Normal decode])
	Physical Slot: 1
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 32 bytes
	Interrupt: pin A routed to IRQ 16
	NUMA node: 0
	Bus: primary=05, secondary=06, subordinate=06, sec-latency=64
	I/O behind bridge: 0000e000-0000efff
	Memory behind bridge: fb400000-fb4fffff
	Prefetchable memory behind bridge: fff00000-000fffff
	Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: <access denied>

06:00.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (prog-if 06 [16950])
	Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart)
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 16
	NUMA node: 0
	Region 0: I/O ports at e0e0 [size=32]
	Region 1: Memory at fb407000 (32-bit, non-prefetchable) [size=4K]
	Region 2: I/O ports at e0c0 [size=32]
	Region 3: Memory at fb406000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: <access denied>
	Kernel driver in use: serial

06:00.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled)
	Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled)
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	NUMA node: 0
	Region 0: I/O ports at e0a0 [disabled] [size=32]
	Region 1: Memory at fb405000 (32-bit, non-prefetchable) [disabled] [size=4K]
	Region 2: I/O ports at e080 [disabled] [size=32]
	Region 3: Memory at fb404000 (32-bit, non-prefetchable) [disabled] [size=4K]
	Capabilities: <access denied>

06:01.0 Serial controller: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart) (prog-if 06 [16950])
	Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Uart)
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin A routed to IRQ 17
	NUMA node: 0
	Region 0: I/O ports at e060 [size=32]
	Region 1: Memory at fb403000 (32-bit, non-prefetchable) [size=4K]
	Region 2: I/O ports at e040 [size=32]
	Region 3: Memory at fb402000 (32-bit, non-prefetchable) [size=4K]
	Capabilities: <access denied>
	Kernel driver in use: serial

06:01.1 Bridge: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled)
	Subsystem: Oxford Semiconductor Ltd OX16PCI954 (Quad 16950 UART) function 0 (Disabled)
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	NUMA node: 0
	Region 0: I/O ports at e020 [disabled] [size=32]
	Region 1: Memory at fb401000 (32-bit, non-prefetchable) [disabled] [size=4K]
	Region 2: I/O ports at e000 [disabled] [size=32]
	Region 3: Memory at fb400000 (32-bit, non-prefetchable) [disabled] [size=4K]
	Capabilities: <access denied>


  reply	other threads:[~2020-11-25 13:49 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-20 19:29 [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets Sean V Kelley
2020-02-20 19:29 ` [PATCH v2 1/2] " Sean V Kelley
2020-02-20 19:29 ` [PATCH v2 2/2] Documentation:PCI: Add background on Boot Interrupts Sean V Kelley
2020-02-27 22:49 ` [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets Bjorn Helgaas
     [not found] ` <b2da25c8-121a-b241-c028-68e49bab0081@tik.uni-stuttgart.de>
2020-11-25 11:54   ` boot interrupt quirk (also in 4.19.y) breaks serial ports (was: [PATCH v2 0/2] pci: Add boot interrupt quirk mechanism for Xeon chipsets) Thomas Gleixner
2020-11-25 13:41     ` Stefan Bühler [this message]
2020-11-26 23:45       ` Thomas Gleixner
2020-11-27  9:17         ` Stefan Bühler
2020-11-30 10:48           ` Thomas Gleixner
2022-09-23 19:20   ` Grzegorz Halat

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