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From: Vidya Sagar <vidyas@nvidia.com>
To: Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>,
	"jingoohan1@gmail.com" <jingoohan1@gmail.com>,
	"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	"amurray@thegoodpenguin.co.uk" <amurray@thegoodpenguin.co.uk>,
	"robh@kernel.org" <robh@kernel.org>,
	"thierry.reding@gmail.com" <thierry.reding@gmail.com>,
	"jonathanh@nvidia.com" <jonathanh@nvidia.com>,
	<alan.mikhak@sifive.com>, <kishon@ti.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"kthota@nvidia.com" <kthota@nvidia.com>,
	"mmaddireddy@nvidia.com" <mmaddireddy@nvidia.com>,
	"sagar.tv@gmail.com" <sagar.tv@gmail.com>
Subject: Re: [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory separately
Date: Mon, 6 Jul 2020 10:05:06 +0530
Message-ID: <dd32f413-aa1c-b2e6-d76f-9d2897a8cfad@nvidia.com> (raw)
In-Reply-To: <389018aa-79c8-4a1e-5379-8b8e42939859@nvidia.com>



On 18-Jun-20 12:26 AM, Vidya Sagar wrote:
> 
> 
> On 02-Jun-20 10:37 PM, Gustavo Pimentel wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On Tue, Jun 2, 2020 at 11:9:38, Vidya Sagar <vidyas@nvidia.com> wrote:
>>
>>> In this patch series,
>>> Patch-1
>>> adds required infrastructure to deal with prefetchable memory region
>>> information coming from 'ranges' property of the respective 
>>> device-tree node
>>> separately from non-prefetchable memory region information.
>>> Patch-2
>>> Adds support to use ATU region-3 for establishing the mapping between 
>>> CPU
>>> addresses and PCIe bus addresses.
>>> It also changes the logic to determine whether mapping is required or 
>>> not by
>>> checking both CPU address and PCIe bus address for both prefetchable and
>>> non-prefetchable regions. If the addresses are same, then, it is 
>>> understood
>>> that 1:1 mapping is in place and there is no need to setup ATU mapping
>>> whereas if the addresses are not the same, then, there is a need to 
>>> setup ATU
>>> mapping. This is certainly true for Tegra194 and what I heard from 
>>> our HW
>>> engineers is that it should generally be true for any DWC based 
>>> implementation
>>> also.
>>> Hence, I request Synopsys folks (Jingoo Han & Gustavo Pimentel ??) to 
>>> confirm
>>> the same so that this particular patch won't cause any regressions 
>>> for other
>>> DWC based platforms.
>>
>> Hi Vidya,
>>
>> Unfortunately due to the COVID-19 lockdown, I can't access my development
>> prototype setup to test your patch.
>> It might take some while until I get the possibility to get access to it
>> again.
> Hi Gustavo,
> Did you find time to check this?
> Adding Kishon and Alan as well to take a look at this and verify on 
> their platforms if possible.
Hi Kishon and Alan, did you find time to verify this on your respective 
platforms?

Thanks,
Vidya Sagar
> 
> Thanks,
> Vidya Sagar
> 
>>
>> -Gustavo
>>
>>>
>>> Vidya Sagar (2):
>>>    PCI: dwc: Add support to handle prefetchable memory separately
>>>    PCI: dwc: Use ATU region to map prefetchable memory region
>>>
>>>   .../pci/controller/dwc/pcie-designware-host.c | 46 ++++++++++++++-----
>>>   drivers/pci/controller/dwc/pcie-designware.c  |  6 ++-
>>>   drivers/pci/controller/dwc/pcie-designware.h  |  8 +++-
>>>   3 files changed, 45 insertions(+), 15 deletions(-)
>>>
>>> -- 
>>> 2.17.1
>>
>>

      parent reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-02 10:09 Vidya Sagar
2020-06-02 10:09 ` [PATCH 1/2] " Vidya Sagar
2020-07-29 18:56   ` Rob Herring
2020-06-02 10:09 ` [PATCH 2/2] PCI: dwc: Use ATU region to map prefetchable memory region Vidya Sagar
2020-06-02 17:07 ` [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory separately Gustavo Pimentel
2020-06-17 18:56   ` Vidya Sagar
2020-06-17 21:14     ` Gustavo Pimentel
2020-07-06  4:35     ` Vidya Sagar [this message]

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